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/*
* at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* 3 MMC ports
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
/ {
ahb {
apb {
pinctrl@fffff200 {
mmc2 {
pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
atmel,pins =
<AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
};
pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
atmel,pins =
<AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
};
};
};
pmc: pmc@fffffc00 {
periphck {
mci2_clk: mci2_clk {
#clock-cells = <0>;
reg = <23>;
};
};
};
mmc2: mmc@f8004000 {
compatible = "atmel,hsmci";
reg = <0xf8004000 0x600>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
dma-names = "rxtx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
clocks = <&mci2_clk>;
clock-names = "mci_clk";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
};
};
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