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| author | Ingo Molnar <mingo@elte.hu> | 2010-05-08 04:02:57 -0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-05-08 04:02:57 -0400 |
| commit | ed82702155b6343727ee732f7eae6d72e8b453fe (patch) | |
| tree | c0925890e9b917d456d0fec38f0d64dad8a99b93 /tools | |
| parent | 4d1c52b02d977d884abb21d0bbaba6b5d6bc8374 (diff) | |
| parent | 1cf4a0632c24ea61162ed819bde358bc94c55510 (diff) | |
Merge branch 'perf' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux-2.6 into perf/core
Diffstat (limited to 'tools')
| -rw-r--r-- | tools/perf/Documentation/perf-list.txt | 19 | ||||
| -rw-r--r-- | tools/perf/util/parse-events.c | 3 |
2 files changed, 18 insertions, 4 deletions
diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt index ad765e0b8860..43e3dd284b90 100644 --- a/tools/perf/Documentation/perf-list.txt +++ b/tools/perf/Documentation/perf-list.txt | |||
| @@ -18,8 +18,16 @@ various perf commands with the -e option. | |||
| 18 | RAW HARDWARE EVENT DESCRIPTOR | 18 | RAW HARDWARE EVENT DESCRIPTOR |
| 19 | ----------------------------- | 19 | ----------------------------- |
| 20 | Even when an event is not available in a symbolic form within perf right now, | 20 | Even when an event is not available in a symbolic form within perf right now, |
| 21 | it can be encoded as <UMASK VALUE><EVENT NUM>, for instance, if the Intel docs | 21 | it can be encoded in a per processor specific way. |
| 22 | describe an event as: | 22 | |
| 23 | For instance For x86 CPUs NNN represents the raw register encoding with the | ||
| 24 | layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout | ||
| 25 | of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, | ||
| 26 | Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). | ||
| 27 | |||
| 28 | Example: | ||
| 29 | |||
| 30 | If the Intel docs for a QM720 Core i7 describe an event as: | ||
| 23 | 31 | ||
| 24 | Event Umask Event Mask | 32 | Event Umask Event Mask |
| 25 | Num. Value Mnemonic Description Comment | 33 | Num. Value Mnemonic Description Comment |
| @@ -33,6 +41,9 @@ raw encoding of 0x1A8 can be used: | |||
| 33 | perf stat -e r1a8 -a sleep 1 | 41 | perf stat -e r1a8 -a sleep 1 |
| 34 | perf record -e r1a8 ... | 42 | perf record -e r1a8 ... |
| 35 | 43 | ||
| 44 | You should refer to the processor specific documentation for getting these | ||
| 45 | details. Some of them are referenced in the SEE ALSO section below. | ||
| 46 | |||
| 36 | OPTIONS | 47 | OPTIONS |
| 37 | ------- | 48 | ------- |
| 38 | None | 49 | None |
| @@ -40,4 +51,6 @@ None | |||
| 40 | SEE ALSO | 51 | SEE ALSO |
| 41 | -------- | 52 | -------- |
| 42 | linkperf:perf-stat[1], linkperf:perf-top[1], | 53 | linkperf:perf-stat[1], linkperf:perf-top[1], |
| 43 | linkperf:perf-record[1] | 54 | linkperf:perf-record[1], |
| 55 | http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide], | ||
| 56 | http://support.amd.com/us/Processor_TechDocs/24593.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming] | ||
diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index ae7f5917935c..9bf0f402ca73 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c | |||
| @@ -943,7 +943,8 @@ void print_events(void) | |||
| 943 | 943 | ||
| 944 | printf("\n"); | 944 | printf("\n"); |
| 945 | printf(" %-42s [%s]\n", | 945 | printf(" %-42s [%s]\n", |
| 946 | "rNNN (NNN=<UMASK VALUE><EVENT NUM>)", event_type_descriptors[PERF_TYPE_RAW]); | 946 | "rNNN (see 'perf list --help' on how to encode it)", |
| 947 | event_type_descriptors[PERF_TYPE_RAW]); | ||
| 947 | printf("\n"); | 948 | printf("\n"); |
| 948 | 949 | ||
| 949 | printf(" %-42s [%s]\n", | 950 | printf(" %-42s [%s]\n", |
