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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-06-01 11:16:20 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-06-04 08:00:09 -0400
commit7c62a164faea430c6e4c411eb0870640cf51a6e5 (patch)
tree487f1bd6f9893a24b3cac55e36784d7f01ee51a9 /tools/virtio
parent2bd89a07db684573d2fce0d5148103c3dcfb0873 (diff)
drm/i915: refactor cpu eDP PLL handling a bit
This prepares a bit for the next big patch, where we switch the semantics of the different clocks in the pipe config around. Since I've broken cpu eDP PLL handling in the first version I've figured some refactoring is in order. Split out on request from Paulo Zanoni. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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