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The LITMUS^RT kernel.

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author	Linus Torvalds <torvalds@linux-foundation.org>	2014-11-02 13:28:43 -0500
committer	Linus Torvalds <torvalds@linux-foundation.org>	2014-11-02 13:28:43 -0500
commit	7e05b807b93cc553bc2aa5ae8fac620cece34720 (patch)
tree	6240b09f201c210d7e3f5cd46086a64852530de2 /tools/perf/scripts/python
parent	4cb8c3593bbb884c5c282b1d8502a0930235fe88 (diff)
parent	9f2f7d4c8dfcf4617af5de6ea381b91deac3db48 (diff)

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

Pull VFS fixes from Al Viro: "A bunch of assorted fixes, most of them followups to overlayfs merge" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: ovl: initialize ->is_cursor Return short read or 0 at end of a raw device, not EIO isofs: don't bother with ->d_op for normal case isofs_cmp(): we'll never see a dentry for . or .. overlayfs: fix lockdep misannotation ovl: fix check for cursor overlayfs: barriers for opening upper-layer directory rcu: Provide counterpart to rcu_dereference() for non-RCU situations staging: android: logger: Fix log corruption regression

Diffstat (limited to 'tools/perf/scripts/python')

0 files changed, 0 insertions, 0 deletions

} dwpci->pdev = pdev; dws = &dwpci->dws; /* Get basic io resource and map it */ dws->paddr = pci_resource_start(pdev, pci_bar); dws->iolen = pci_resource_len(pdev, pci_bar); ret = pci_request_region(pdev, pci_bar, dev_name(&pdev->dev)); if (ret) goto err_kfree; dws->regs = ioremap_nocache((unsigned long)dws->paddr, pci_resource_len(pdev, pci_bar)); if (!dws->regs) { ret = -ENOMEM; goto err_release_reg; } dws->parent_dev = &pdev->dev; dws->bus_num = 0; dws->num_cs = 4; dws->irq = pdev->irq; /* * Specific handling for Intel MID paltforms, like dma setup, * clock rate, FIFO depth. */ if (pdev->device == 0x0800) { ret = dw_spi_mid_init(dws); if (ret) goto err_unmap; } ret = dw_spi_add_host(dws); if (ret) goto err_unmap; /* PCI hook and SPI hook use the same drv data */ pci_set_drvdata(pdev, dwpci); return 0; err_unmap: iounmap(dws->regs); err_release_reg: pci_release_region(pdev, pci_bar); err_kfree: kfree(dwpci); err_disable: pci_disable_device(pdev); return ret; } static void __devexit spi_pci_remove(struct pci_dev *pdev) { struct dw_spi_pci *dwpci = pci_get_drvdata(pdev); pci_set_drvdata(pdev, NULL); dw_spi_remove_host(&dwpci->dws); iounmap(dwpci->dws.regs); pci_release_region(pdev, 0); kfree(dwpci); pci_disable_device(pdev); } #ifdef CONFIG_PM static int spi_suspend(struct pci_dev *pdev, pm_message_t state) { struct dw_spi_pci *dwpci = pci_get_drvdata(pdev); int ret; ret = dw_spi_suspend_host(&dwpci->dws); if (ret) return ret; pci_save_state(pdev); pci_disable_device(pdev); pci_set_power_state(pdev, pci_choose_state(pdev, state)); return ret; } static int spi_resume(struct pci_dev *pdev) { struct dw_spi_pci *dwpci = pci_get_drvdata(pdev); int ret; pci_set_power_state(pdev, PCI_D0); pci_restore_state(pdev); ret = pci_enable_device(pdev); if (ret) return ret; return dw_spi_resume_host(&dwpci->dws); } #else #define spi_suspend NULL #define spi_resume NULL #endif static const struct pci_device_id pci_ids[] __devinitdata = { /* Intel MID platform SPI controller 0 */ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) }, {}, }; static struct pci_driver dw_spi_driver = { .name = DRIVER_NAME, .id_table = pci_ids, .probe = spi_pci_probe, .remove = __devexit_p(spi_pci_remove), .suspend = spi_suspend, .resume = spi_resume, }; static int __init mrst_spi_init(void) { return pci_register_driver(&dw_spi_driver); } static void __exit mrst_spi_exit(void) { pci_unregister_driver(&dw_spi_driver); } module_init(mrst_spi_init); module_exit(mrst_spi_exit); MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); MODULE_DESCRIPTION("PCI interface driver for DW SPI Core"); MODULE_LICENSE("GPL v2");