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| author | Fujinaka, Todd <todd.fujinaka@intel.com> | 2014-03-13 00:29:01 -0400 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2014-03-21 06:00:49 -0400 |
| commit | 22a8b2915998a5f35f659c1d419bd4bcbb1b6f41 (patch) | |
| tree | 4a6f743aef13954e41acfada8bdf07e9cb6c4762 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 6ab5f7b2981e842e318ff48c708aaaa2a5a6a43e (diff) | |
igb: add register rd/wr for surprise removal
Add initial register rd/wr for surprise removal (LER).
Signed-off-by: Todd Fujinaka <todd.fujinaka@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions