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| author | Haojian Zhuang <haojian.zhuang@gmail.com> | 2013-12-11 00:07:55 -0500 |
|---|---|---|
| committer | Haojian Zhuang <haojian.zhuang@gmail.com> | 2013-12-11 03:42:23 -0500 |
| commit | ea010e5188dab61b64c1ad0221adc271039e7775 (patch) | |
| tree | 88f3aaf6122d5d8acf0eb50b3839a84f62fe62ba /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 5e39edd48543c2cc80a28e265b83003737088929 (diff) | |
clk: hi3620: add gate clock flag
Add missing CLK_SET_RATE_PARENT flag for gate clock.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions