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authorAlan Stern <stern@rowland.harvard.edu>2013-01-25 16:54:22 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-01-25 16:58:20 -0500
commit6e0c3339a6f19d748f16091d0a05adeb1e1f822b (patch)
tree0afaafdaaaca7df3362dde760b7d0273f508f04f /tools/perf/scripts/python/syscall-counts-by-pid.py
parent55bcdce8a8228223ec4d17d8ded8134ed265d2c5 (diff)
USB: EHCI: unlink one async QH at a time
This patch (as1648) fixes a regression affecting nVidia EHCI controllers. Evidently they don't like to have more than one async QH unlinked at a time. I can't imagine how they manage to mess it up, but at least one of them does. The patch changes the async unlink logic in two ways: Each time an IAA cycle is started, only the first QH on the async unlink list is handled (rather than all of them). Async QHs do not all get unlinked as soon as they have been empty for long enough. Instead, only the last one (i.e., the one that has been on the schedule the longest) is unlinked, and then only if no other unlinks are in progress at the time. This means that when multiple QHs are empty, they won't be unlinked as quickly as before. That's okay; it won't affect correct operation of the driver or add an excessive load. Multiple unlinks tend to be relatively rare in any case. Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Reported-and-tested-by: Piergiorgio Sartor <piergiorgio.sartor@nexgo.de> Cc: stable <stable@vger.kernel.org> # 3.6 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions
MU_H #define _ASMARM_PGTABLE_NOMMU_H #ifndef __ASSEMBLY__ #include <linux/slab.h> #include <asm/processor.h> #include <asm/page.h> #include <asm/io.h> /* * Trivial page table functions. */ #define pgd_present(pgd) (1) #define pgd_none(pgd) (0) #define pgd_bad(pgd) (0) #define pgd_clear(pgdp) #define kern_addr_valid(addr) (1) #define pmd_offset(a, b) ((void *)0) /* FIXME */ /* * PMD_SHIFT determines the size of the area a second-level page table can map * PGDIR_SHIFT determines what a third-level page table entry can map */ #define PGDIR_SHIFT 21 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) /* FIXME */ #define PAGE_NONE __pgprot(0) #define PAGE_SHARED __pgprot(0) #define PAGE_COPY __pgprot(0) #define PAGE_READONLY __pgprot(0) #define PAGE_KERNEL __pgprot(0) #define swapper_pg_dir ((pgd_t *) 0) #define __swp_type(x) (0) #define __swp_offset(x) (0) #define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) }) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) typedef pte_t *pte_addr_t; static inline int pte_file(pte_t pte) { return 0; } /* * ZERO_PAGE is a global shared page that is always zero: used * for zero-mapped memory areas etc.. */ #define ZERO_PAGE(vaddr) (virt_to_page(0)) /* * Mark the prot value as uncacheable and unbufferable. */ #define pgprot_noncached(prot) __pgprot(0) #define pgprot_writecombine(prot) __pgprot(0) /* * These would be in other places but having them here reduces the diffs. */ extern unsigned int kobjsize(const void *objp); extern int is_in_rom(unsigned long); /* * No page table caches to initialise. */ #define pgtable_cache_init() do { } while (0) #define io_remap_page_range remap_page_range #define io_remap_pfn_range remap_pfn_range #define MK_IOSPACE_PFN(space, pfn) (pfn) #define GET_IOSPACE(pfn) 0 #define GET_PFN(pfn) (pfn) /* * All 32bit addresses are effectively valid for vmalloc... * Sort of meaningless for non-VM targets. */ #define VMALLOC_START 0 #define VMALLOC_END 0xffffffff #define FIRST_USER_ADDRESS (0) #else /* * dummy tlb and user structures. */ #define v3_tlb_fns (0) #define v4_tlb_fns (0) #define v4wb_tlb_fns (0) #define v4wbi_tlb_fns (0) #define v6_tlb_fns (0) #define v3_user_fns (0) #define v4_user_fns (0) #define v4_mc_user_fns (0) #define v4wb_user_fns (0) #define v4wt_user_fns (0) #define v6_user_fns (0) #define xscale_mc_user_fns (0) #endif /*__ASSEMBLY__*/ #endif /* _ASMARM_PGTABLE_H */