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authorDong Aisheng <b29396@freescale.com>2013-10-18 07:48:46 -0400
committerChris Ball <chris@printf.net>2013-10-21 15:58:10 -0400
commitde5bdbffd89dea0e3de76f99b0b036422bb93686 (patch)
tree25ba1c08549c4e8c44171184d31e81f9af82d37d /tools/perf/scripts/python/export-to-postgresql.py
parent114f2bf6a158cd84c1a7280cf6233904c8bce430 (diff)
mmc: sdhci-esdhc-imx: add DDR mode support for mx6
When DDR mode is enabled, the initial pre_div should be 2. And the pre_div value should be changed accordingly from ... 02h) Base clock divided by 4 01h) Base clock divided by 2 00h) Base clock divided by 1 to .. 02h) Base clock divided by 8 01h) Base clock divided by 4 00h) Base clock divided by 2 Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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