litmus-rt.git - The LITMUS^RT kernel.

The LITMUS^RT kernel.

Bjoern Brandenburg

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author	Alan Cox <alan@linux.intel.com>	2012-12-18 17:21:30 -0500
committer	Linus Torvalds <torvalds@linux-foundation.org>	2012-12-18 18:02:12 -0500
commit	3012d60b39761b0bf73e3be677d2f8e424f0b294 (patch)
tree	2db37054681113058b4e369dce36f41be8c85020 /tools/perf/scripts/python/export-to-postgresql.py
parent	d95bfe464bae35daadaa46477e3ef984747abfff (diff)

drivers/message/fusion/mptscsih.c: missing break

This happens to do the right thing in all cases on fibre channel but not on other media types Signed-off-by: Alan Cox <alan@linux.intel.com> Cc: James Bottomley <James.Bottomley@HansenPartnership.com> Cc: Nagalakshmi Nandigama <nagalakshmi.nandigama@lsi.com> Cc: Kashyap Desai <kashyap.desai@lsi.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')

0 files changed, 0 insertions, 0 deletions

00002) #define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0) #define HW_ATL_B0_TXD_CTL_DD (0x00100000) #define HW_ATL_B0_TXD_CTL_EOP (0x00200000) #define HW_ATL_B0_TXD_CTL_CMD_X (0x3FC00000) #define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22) #define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23) #define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24) #define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25) #define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26) #define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27) #define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28) #define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21) #define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22) #define HW_ATL_B0_MPI_CONTROL_ADR 0x0368U #define HW_ATL_B0_MPI_STATE_ADR 0x036CU #define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU #define HW_ATL_B0_MPI_SPEED_SHIFT 16U #define HW_ATL_B0_TXBUF_MAX 160U #define HW_ATL_B0_RXBUF_MAX 320U #define HW_ATL_B0_RSS_REDIRECTION_MAX 64U #define HW_ATL_B0_RSS_REDIRECTION_BITS 3U #define HW_ATL_B0_RSS_HASHKEY_BITS 320U #define HW_ATL_B0_TCRSS_4_8 1 #define HW_ATL_B0_TC_MAX 1U #define HW_ATL_B0_RSS_MAX 8U #define HW_ATL_B0_LRO_RXD_MAX 2U #define HW_ATL_B0_RS_SLIP_ENABLED 0U /* (256k -1(max pay_len) - 54(header)) */ #define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE 262089U /* (256k -1(max pay_len) - 74(header)) */ #define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE 262069U #define HW_ATL_B0_CHIP_REVISION_B0 0xA0U #define HW_ATL_B0_CHIP_REVISION_UNKNOWN 0xFFU #define HW_ATL_B0_FW_SEMA_RAM 0x2U #define HW_ATL_B0_TXC_LEN_TUNLEN (0x0000FF00) #define HW_ATL_B0_TXC_LEN_OUTLEN (0xFFFF0000) #define HW_ATL_B0_TXC_CTL_DESC_TYPE (0x00000007) #define HW_ATL_B0_TXC_CTL_CTX_ID (0x00000008) #define HW_ATL_B0_TXC_CTL_VLAN (0x000FFFF0) #define HW_ATL_B0_TXC_CTL_CMD (0x00F00000) #define HW_ATL_B0_TXC_CTL_L2LEN (0x7F000000) #define HW_ATL_B0_TXC_CTL_L3LEN (0x80000000) /* L3LEN lsb */ #define HW_ATL_B0_TXC_LEN2_L3LEN (0x000000FF) /* L3LE upper bits */ #define HW_ATL_B0_TXC_LEN2_L4LEN (0x0000FF00) #define HW_ATL_B0_TXC_LEN2_MSSLEN (0xFFFF0000) #define HW_ATL_B0_RXD_DD (0x1) #define HW_ATL_B0_RXD_NCEA0 (0x1) #define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F) #define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0) #define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000) #define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000) #define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000) #define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001) #define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002) #define HW_ATL_B0_RXD_WB_STAT2_RXSTAT (0x003C) #define HW_ATL_B0_RXD_WB_STAT2_MACERR (0x0004) #define HW_ATL_B0_RXD_WB_STAT2_IP4ERR (0x0008) #define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR (0x0010) #define HW_ATL_B0_RXD_WB_STAT2_RXESTAT (0x0FC0) #define HW_ATL_B0_RXD_WB_STAT2_RSCCNT (0xF000) #define L2_FILTER_ACTION_DISCARD (0x0) #define L2_FILTER_ACTION_HOST (0x1) #define HW_ATL_B0_UCP_0X370_REG (0x370) #define HW_ATL_B0_FLUSH() AQ_HW_READ_REG(self, 0x10) #define HW_ATL_B0_FW_VER_EXPECTED 0x01050006U #define HW_ATL_INTR_MODER_MAX 0x1FF #define HW_ATL_INTR_MODER_MIN 0xFF /* HW layer capabilities */ static struct aq_hw_caps_s hw_atl_b0_hw_caps_ = { .ports = 1U, .is_64_dma = true, .msix_irqs = 4U, .irq_mask = ~0U, .vecs = HW_ATL_B0_RSS_MAX, .tcs = HW_ATL_B0_TC_MAX, .rxd_alignment = 1U, .rxd_size = HW_ATL_B0_RXD_SIZE, .rxds = 8U * 1024U, .txd_alignment = 1U, .txd_size = HW_ATL_B0_TXD_SIZE, .txds = 8U * 1024U, .txhwb_alignment = 4096U, .tx_rings = HW_ATL_B0_TX_RINGS, .rx_rings = HW_ATL_B0_RX_RINGS, .hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_SG | NETIF_F_TSO | NETIF_F_LRO, .hw_priv_flags = IFF_UNICAST_FLT, .link_speed_msk = (AQ_NIC_RATE_10G | AQ_NIC_RATE_5G | AQ_NIC_RATE_2GS | AQ_NIC_RATE_1G | AQ_NIC_RATE_100M), .flow_control = true, .mtu = HW_ATL_B0_MTU_JUMBO, .mac_regs_count = 88, .fw_ver_expected = HW_ATL_B0_FW_VER_EXPECTED, }; #endif /* HW_ATL_B0_INTERNAL_H */


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