diff options
| author | Vivek Gautam <gautam.vivek@samsung.com> | 2014-11-21 08:35:47 -0500 |
|---|---|---|
| committer | Felipe Balbi <balbi@ti.com> | 2014-11-21 10:07:29 -0500 |
| commit | ed692a99f31c92ec649ee2f7a0ecb4aa0f69d853 (patch) | |
| tree | baf45a59d5289368df477658c2a2b3b882424b37 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 72d996fc7a01c2e4d581a15db7d001e2799ffb29 (diff) | |
usb: dwc3: exynos: Add provision for AXI UpScaler clock on exynos7
DWC3 controller on Exynos7 SoC has separate control for
AXI UpScaler which connects DWC3 DRD controller to AXI bus.
Get the gate clock for the same to control it across power
cycles.
Suggested-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions