diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-06-27 19:04:08 -0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-08-08 11:43:28 -0400 |
| commit | 5d6f7ea752228788eddce0b9e268fa1f0eabdd7f (patch) | |
| tree | 2fa7b87dc26a81281bdbc9bf24a190e3f915eb1f /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 4811ff4f2388727a161ea49c2b0ddca95e44c7f9 (diff) | |
drm/i915: Add chv cmnlane power wells
CHV has two display PHYs so there are also two cmnlane power wells. Add
the approriate code to power the wells up/down.
Like on VLV we do the cmnreset assert/deassert and the DPLL refclock
enabling at approriate times.
This code actually works on my bsw.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions