litmus-rt.git - The LITMUS^RT kernel.

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author	Linus Torvalds <torvalds@linux-foundation.org>	2010-09-10 10:24:51 -0400
committer	Linus Torvalds <torvalds@linux-foundation.org>	2010-09-10 10:24:51 -0400
commit	6ccaa3172941c0a97c7f1c5155b1d32ecd27ec2f (patch)
tree	f92588c8084f758c348120d712292d7f4a00edc7 /tools/perf/scripts/python/Perf-Trace-Util/Context.c
parent	3657423c02b639fcade37673f8541bd90c5e58e5 (diff)
parent	4deb22a6001eb0d4058295c3645c36190a0ec603 (diff)

Merge branch 'at91-fixes-for-linus' of git://github.com/at91linux/linux-2.6-at91

* 'at91-fixes-for-linus' of git://github.com/at91linux/linux-2.6-at91: AT91: at91sam9261ek: remove C99 comments but keep information AT91: at91sam9261ek board: remove warnings related to use of SPI or SD/MMC AT91: dm9000 initialization update AT91: SAM9G45 - add a separate clock entry for every single TC block AT91: clock: peripheral clocks can have other parent than mck AT91: change dma resource index

Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/Context.c')

0 files changed, 0 insertions, 0 deletions

/* * linux/drivers/net/irda/pxaficp_ir.c * * Based on sa1100_ir.c by Russell King * * Changes copyright (C) 2003-2005 MontaVista Software, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Infra-red driver (SIR/FIR) for the PXA2xx embedded microprocessor * */ #include <linux/module.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/gpio.h> #include <net/irda/irda.h> #include <net/irda/irmod.h> #include <net/irda/wrapper.h> #include <net/irda/irda_device.h> #include <mach/dma.h> #include <mach/irda.h> #include <mach/regs-uart.h> #include <mach/regs-ost.h> #define FICP __REG(0x40800000) /* Start of FICP area */ #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ #define ICDR __REG(0x4080000c) /* ICP Data Register */ #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ #define ICCR0_AME (1 << 7) /* Address match enable */ #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ #define ICCR0_RXE (1 << 4) /* Receive enable */ #define ICCR0_TXE (1 << 3) /* Transmit enable */ #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ #define ICCR0_LBM (1 << 1) /* Loopback mode */ #define ICCR0_ITR (1 << 0) /* IrDA transmission */ #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ #ifdef CONFIG_PXA27x #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ #endif #define ICSR0_FRE (1 << 5) /* Framing error */ #define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ #define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ #define ICSR0_RAB (1 << 2) /* Receiver abort */ #define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ #define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ #define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ #define ICSR1_CRE (1 << 5) /* CRC error */ #define ICSR1_EOF (1 << 4) /* End of frame */ #define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ #define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ #define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ #define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ #define IrSR_RXPL_NEG_IS_ZERO (1<<4) #define IrSR_RXPL_POS_IS_ZERO 0x0 #define IrSR_TXPL_NEG_IS_ZERO (1<<3) #define IrSR_TXPL_POS_IS_ZERO 0x0 #define IrSR_XMODE_PULSE_1_6 (1<<2) #define IrSR_XMODE_PULSE_3_16 0x0 #define IrSR_RCVEIR_IR_MODE (1<<1) #define IrSR_RCVEIR_UART_MODE 0x0 #define IrSR_XMITIR_IR_MODE (1<<0) #define IrSR_XMITIR_UART_MODE 0x0 #define IrSR_IR_RECEIVE_ON (\ IrSR_RXPL_NEG_IS_ZERO | \ IrSR_TXPL_POS_IS_ZERO | \ IrSR_XMODE_PULSE_3_16 | \ IrSR_RCVEIR_IR_MODE | \ IrSR_XMITIR_UART_MODE) #define IrSR_IR_TRANSMIT_ON (\ IrSR_RXPL_NEG_IS_ZERO | \ IrSR_TXPL_POS_IS_ZERO | \ IrSR_XMODE_PULSE_3_16 | \ IrSR_RCVEIR_UART_MODE | \ IrSR_XMITIR_IR_MODE) struct pxa_irda { int speed; int newspeed; unsigned long last_oscr; unsigned char *dma_rx_buff; unsigned char *dma_tx_buff; dma_addr_t dma_rx_buff_phy; dma_addr_t dma_tx_buff_phy; unsigned int dma_tx_buff_len; int txdma; int rxdma; struct irlap_cb *irlap; struct qos_info qos; iobuff_t tx_buff; iobuff_t rx_buff; struct device *dev; struct pxaficp_platform_data *pdata; struct clk *fir_clk; struct clk *sir_clk; struct clk *cur_clk; }; static inline void pxa_irda_disable_clk(struct pxa_irda *si) { if (si->cur_clk) clk_disable(si->cur_clk); si->cur_clk = NULL; } static inline void pxa_irda_enable_firclk(struct pxa_irda *si) { si->cur_clk = si->fir_clk; clk_enable(si->fir_clk); } static inline void pxa_irda_enable_sirclk(struct pxa_irda *si) { si->cur_clk = si->sir_clk; clk_enable(si->sir_clk); } #define IS_FIR(si) ((si)->speed >= 4000000) #define IRDA_FRAME_SIZE_LIMIT 2047 inline static void pxa_irda_fir_dma_rx_start(struct pxa_irda *si) { DCSR(si->rxdma) = DCSR_NODESC; DSADR(si->rxdma) = __PREG(ICDR); DTADR(si->rxdma) = si->dma_rx_buff_phy; DCMD(si->rxdma) = DCMD_INCTRGADDR | DCMD_FLOWSRC | DCMD_WIDTH1 | DCMD_BURST32 | IRDA_FRAME_SIZE_LIMIT; DCSR(si->rxdma) |= DCSR_RUN; } inline static void pxa_irda_fir_dma_tx_start(struct pxa_irda *si) { DCSR(si->txdma) = DCSR_NODESC; DSADR(si->txdma) = si->dma_tx_buff_phy; DTADR(si->txdma) = __PREG(ICDR); DCMD(si->txdma) = DCMD_INCSRCADDR | DCMD_FLOWTRG | DCMD_ENDIRQEN | DCMD_WIDTH1 | DCMD_BURST32 | si->dma_tx_buff_len; DCSR(si->txdma) |= DCSR_RUN; } /* * Set the IrDA communications mode. */ static void pxa_irda_set_mode(struct pxa_irda *si, int mode) { if (si->pdata->transceiver_mode) si->pdata->transceiver_mode(si->dev, mode); else { if (gpio_is_valid(si->pdata->gpio_pwdown)) gpio_set_value(si->pdata->gpio_pwdown, !(mode & IR_OFF) ^ !si->pdata->gpio_pwdown_inverted); pxa2xx_transceiver_mode(si->dev, mode); } } /* * Set the IrDA communications speed. */ static int pxa_irda_set_speed(struct pxa_irda *si, int speed) { unsigned long flags; unsigned int divisor; switch (speed) { case 9600: case 19200: case 38400: case 57600: case 115200: /* refer to PXA250/210 Developer's Manual 10-7 */ /* BaudRate = 14.7456 MHz / (16*Divisor) */ divisor = 14745600 / (16 * speed); local_irq_save(flags); if (IS_FIR(si)) { /* stop RX DMA */ DCSR(si->rxdma) &= ~DCSR_RUN; /* disable FICP */ ICCR0 = 0; pxa_irda_disable_clk(si); /* set board transceiver to SIR mode */ pxa_irda_set_mode(si, IR_SIRMODE); /* enable the STUART clock */ pxa_irda_enable_sirclk(si); } /* disable STUART first */ STIER = 0; /* access DLL & DLH */ STLCR |= LCR_DLAB; STDLL = divisor & 0xff; STDLH = divisor >> 8; STLCR &= ~LCR_DLAB; si->speed = speed; STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6; STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE; local_irq_restore(flags); break; case 4000000: local_irq_save(flags); /* disable STUART */ STIER = 0; STISR = 0; pxa_irda_disable_clk(si); /* disable FICP first */ ICCR0 = 0; /* set board transceiver to FIR mode */ pxa_irda_set_mode(si, IR_FIRMODE); /* enable the FICP clock */ pxa_irda_enable_firclk(si); si->speed = speed; pxa_irda_fir_dma_rx_start(si); ICCR0 = ICCR0_ITR | ICCR0_RXE; local_irq_restore(flags); break; default: return -EINVAL; } return 0; } /* SIR interrupt service routine. */ static irqreturn_t pxa_irda_sir_irq(int irq, void *dev_id) { struct net_device *dev = dev_id; struct pxa_irda *si = netdev_priv(dev); int iir, lsr, data; iir = STIIR; switch (iir & 0x0F) { case 0x06: /* Receiver Line Status */ lsr = STLSR; while (lsr & LSR_FIFOE) { data = STRBR; if (lsr & (LSR_OE | LSR_PE | LSR_FE | LSR_BI)) { printk(KERN_DEBUG "pxa_ir: sir receiving error\n"); dev->stats.rx_errors++; if (lsr & LSR_FE) dev->stats.rx_frame_errors++; if (lsr & LSR_OE) dev->stats.rx_fifo_errors++; } else { dev->stats.rx_bytes++; async_unwrap_char(dev, &dev->stats, &si->rx_buff, data); } lsr = STLSR; } si->last_oscr = OSCR; break; case 0x04: /* Received Data Available */ /* forth through */ case 0x0C: /* Character Timeout Indication */ do { dev->stats.rx_bytes++; async_unwrap_char(dev, &dev->stats, &si->rx_buff, STRBR); } while (STLSR & LSR_DR); si->last_oscr = OSCR; break; case 0x02: /* Transmit FIFO Data Request */ while ((si->tx_buff.len) && (STLSR & LSR_TDRQ)) { STTHR = *si->tx_buff.data++; si->tx_buff.len -= 1; } if (si->tx_buff.len == 0) { dev->stats.tx_packets++; dev->stats.tx_bytes += si->tx_buff.data - si->tx_buff.head; /* We need to ensure that the transmitter has finished. */ while ((STLSR & LSR_TEMT) == 0) cpu_relax(); si->last_oscr = OSCR; /* * Ok, we've finished transmitting. Now enable * the receiver. Sometimes we get a receive IRQ * immediately after a transmit... */ if (si->newspeed) { pxa_irda_set_speed(si, si->newspeed); si->newspeed = 0; } else { /* enable IR Receiver, disable IR Transmitter */ STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6; /* enable STUART and receive interrupts */ STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE; } /* I'm hungry! */ netif_wake_queue(dev); } break; } return IRQ_HANDLED; } /* FIR Receive DMA interrupt handler */ static void pxa_irda_fir_dma_rx_irq(int channel, void *data) { int dcsr = DCSR(channel); DCSR(channel) = dcsr & ~DCSR_RUN; printk(KERN_DEBUG "pxa_ir: fir rx dma bus error %#x\n", dcsr); } /* FIR Transmit DMA interrupt handler */ static void pxa_irda_fir_dma_tx_irq(int channel, void *data) { struct net_device *dev = data; struct pxa_irda *si = netdev_priv(dev); int dcsr; dcsr = DCSR(channel); DCSR(channel) = dcsr & ~DCSR_RUN; if (dcsr & DCSR_ENDINTR) { dev->stats.tx_packets++; dev->stats.tx_bytes += si->dma_tx_buff_len; } else { dev->stats.tx_errors++; } while (ICSR1 & ICSR1_TBY) cpu_relax(); si->last_oscr = OSCR; /* * HACK: It looks like the TBY bit is dropped too soon. * Without this delay things break. */ udelay(120); if (si->newspeed) { pxa_irda_set_speed(si, si->newspeed); si->newspeed = 0; } else { int i = 64; ICCR0 = 0; pxa_irda_fir_dma_rx_start(si); while ((ICSR1 & ICSR1_RNE) && i--)


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