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author | Robert Richter <robert.richter@amd.com> | 2012-08-07 13:43:15 -0400 |
---|---|---|
committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2012-08-08 11:41:53 -0400 |
commit | 75bc5ca89827fe3f2399321b2920a30bcf658049 (patch) | |
tree | 795933aacb5c9f98613b3c4b8f44cd93f086a366 /tools/perf/Documentation/perf-list.txt | |
parent | 0cf260131c52f681533d17db6fd07545a3dc184e (diff) |
perf list: Update documentation about raw event setup
It was missing that only certain bit fields are passed to the config
value which confused users. Updating it.
Signed-off-by: Robert Richter <robert.richter@amd.com>
Cc: Ingo Molnar <mingo@kernel.org>
Link: http://lkml.kernel.org/r/1344361396-7237-6-git-send-email-robert.richter@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/Documentation/perf-list.txt')
-rw-r--r-- | tools/perf/Documentation/perf-list.txt | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt index ddc22525228d..232be519580a 100644 --- a/tools/perf/Documentation/perf-list.txt +++ b/tools/perf/Documentation/perf-list.txt | |||
@@ -15,6 +15,7 @@ DESCRIPTION | |||
15 | This command displays the symbolic event types which can be selected in the | 15 | This command displays the symbolic event types which can be selected in the |
16 | various perf commands with the -e option. | 16 | various perf commands with the -e option. |
17 | 17 | ||
18 | [[EVENT_MODIFIERS]] | ||
18 | EVENT MODIFIERS | 19 | EVENT MODIFIERS |
19 | --------------- | 20 | --------------- |
20 | 21 | ||
@@ -44,6 +45,11 @@ layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Softwar | |||
44 | of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, | 45 | of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, |
45 | Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). | 46 | Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). |
46 | 47 | ||
48 | Note: Only the following bit fields can be set in x86 counter | ||
49 | registers: event, umask, edge, inv, cmask. Esp. guest/host only and | ||
50 | OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT | ||
51 | MODIFIERS>>. | ||
52 | |||
47 | Example: | 53 | Example: |
48 | 54 | ||
49 | If the Intel docs for a QM720 Core i7 describe an event as: | 55 | If the Intel docs for a QM720 Core i7 describe an event as: |