diff options
author | Mengdong Lin <mengdong.lin@intel.com> | 2012-12-12 09:16:15 -0500 |
---|---|---|
committer | Takashi Iwai <tiwai@suse.de> | 2012-12-12 05:03:12 -0500 |
commit | fa348da53b6ffd3dcebae288d4072a4571755d35 (patch) | |
tree | bcfdb27314cbd6182c499a3fabb22f762241f8a4 /sound | |
parent | 6121b84af33fcec843a082cb6bc8d39f187faa20 (diff) |
ALSA: hda - use usleep_range in link reset and change timeout check
Reducing the time on HDA link reset can help to reduce the driver loading
time. So we replace msleep with usleep_range to get more accurate time
control and change the value to a smaller one. And a 100ms timeout is set
for both entering and exiting the link reset.
Signed-off-by: Xingchao Wang <xingchao.wang@intel.com>
Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound')
-rw-r--r-- | sound/pci/hda/hda_intel.c | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index a9cd18b3db7c..d00dea0eb7f9 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c | |||
@@ -1054,7 +1054,7 @@ static void azx_power_notify(struct hda_bus *bus, bool power_up); | |||
1054 | /* reset codec link */ | 1054 | /* reset codec link */ |
1055 | static int azx_reset(struct azx *chip, int full_reset) | 1055 | static int azx_reset(struct azx *chip, int full_reset) |
1056 | { | 1056 | { |
1057 | int count; | 1057 | unsigned long timeout; |
1058 | 1058 | ||
1059 | if (!full_reset) | 1059 | if (!full_reset) |
1060 | goto __skip; | 1060 | goto __skip; |
@@ -1065,24 +1065,26 @@ static int azx_reset(struct azx *chip, int full_reset) | |||
1065 | /* reset controller */ | 1065 | /* reset controller */ |
1066 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); | 1066 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); |
1067 | 1067 | ||
1068 | count = 50; | 1068 | timeout = jiffies + msecs_to_jiffies(100); |
1069 | while (azx_readb(chip, GCTL) && --count) | 1069 | while (azx_readb(chip, GCTL) && |
1070 | msleep(1); | 1070 | time_before(jiffies, timeout)) |
1071 | usleep_range(500, 1000); | ||
1071 | 1072 | ||
1072 | /* delay for >= 100us for codec PLL to settle per spec | 1073 | /* delay for >= 100us for codec PLL to settle per spec |
1073 | * Rev 0.9 section 5.5.1 | 1074 | * Rev 0.9 section 5.5.1 |
1074 | */ | 1075 | */ |
1075 | msleep(1); | 1076 | usleep_range(500, 1000); |
1076 | 1077 | ||
1077 | /* Bring controller out of reset */ | 1078 | /* Bring controller out of reset */ |
1078 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); | 1079 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); |
1079 | 1080 | ||
1080 | count = 50; | 1081 | timeout = jiffies + msecs_to_jiffies(100); |
1081 | while (!azx_readb(chip, GCTL) && --count) | 1082 | while (!azx_readb(chip, GCTL) && |
1082 | msleep(1); | 1083 | time_before(jiffies, timeout)) |
1084 | usleep_range(500, 1000); | ||
1083 | 1085 | ||
1084 | /* Brent Chartrand said to wait >= 540us for codecs to initialize */ | 1086 | /* Brent Chartrand said to wait >= 540us for codecs to initialize */ |
1085 | msleep(1); | 1087 | usleep_range(1000, 1200); |
1086 | 1088 | ||
1087 | __skip: | 1089 | __skip: |
1088 | /* check to see if controller is ready */ | 1090 | /* check to see if controller is ready */ |