aboutsummaryrefslogtreecommitdiffstats
path: root/sound
diff options
context:
space:
mode:
authorClemens Ladisch <clemens@ladisch.de>2007-12-23 13:50:57 -0500
committerJaroslav Kysela <perex@perex.cz>2008-01-31 11:29:44 -0500
commitd0ce9946c52e7bdf95afb09553775cf28b752254 (patch)
tree684edc99cfd1def12b87abb5431c6b8f0ea2f716 /sound
parenta9b3aa8a0a203b9b62e15c465ba7d4797a6a2c79 (diff)
[ALSA] add CMI8788 driver
Add the snd-oxygen driver for the C-Media CMI8788 (Oxygen) chip, used on the Asound A-8788, AuzenTech X-Meridian, Bgears b-Enspirer, Club3D Theatron DTS, HT-Omega Claro, Razer Barracuda AC-1, Sondigo Inferno, and TempoTec HIFIER sound cards. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
Diffstat (limited to 'sound')
-rw-r--r--sound/pci/Kconfig25
-rw-r--r--sound/pci/Makefile1
-rw-r--r--sound/pci/oxygen/Makefile5
-rw-r--r--sound/pci/oxygen/oxygen.c314
-rw-r--r--sound/pci/oxygen/oxygen.h167
-rw-r--r--sound/pci/oxygen/oxygen_io.c194
-rw-r--r--sound/pci/oxygen/oxygen_lib.c361
-rw-r--r--sound/pci/oxygen/oxygen_mixer.c623
-rw-r--r--sound/pci/oxygen/oxygen_pcm.c726
-rw-r--r--sound/pci/oxygen/oxygen_regs.h246
10 files changed, 2662 insertions, 0 deletions
diff --git a/sound/pci/Kconfig b/sound/pci/Kconfig
index 45f0f6c2f353..d3be87d11259 100644
--- a/sound/pci/Kconfig
+++ b/sound/pci/Kconfig
@@ -183,6 +183,31 @@ config SND_CMIPCI
183 To compile this driver as a module, choose M here: the module 183 To compile this driver as a module, choose M here: the module
184 will be called snd-cmipci. 184 will be called snd-cmipci.
185 185
186config SND_OXYGEN_LIB
187 tristate
188 depends on SND
189 select SND_PCM
190 select SND_MPU401_UART
191
192config SND_OXYGEN
193 tristate "C-Media 8788 (Oxygen)"
194 depends on SND
195 select SND_OXYGEN_LIB
196 help
197 Say Y here to include support for sound cards based on the
198 C-Media CMI8788 (Oxygen HD Audio) chip:
199 * Asound A-8788
200 * AuzenTech X-Meridian
201 * Bgears b-Enspirer
202 * Club3D Theatron DTS
203 * HT-Omega Claro
204 * Razer Barracuda AC-1
205 * Sondigo Inferno
206 * TempoTec HIFIER
207
208 To compile this driver as a module, choose M here: the module
209 will be called snd-oxygen.
210
186config SND_CS4281 211config SND_CS4281
187 tristate "Cirrus Logic (Sound Fusion) CS4281" 212 tristate "Cirrus Logic (Sound Fusion) CS4281"
188 depends on SND 213 depends on SND
diff --git a/sound/pci/Makefile b/sound/pci/Makefile
index 56738da9c14a..2d42fd28f4e7 100644
--- a/sound/pci/Makefile
+++ b/sound/pci/Makefile
@@ -68,6 +68,7 @@ obj-$(CONFIG_SND) += \
68 korg1212/ \ 68 korg1212/ \
69 mixart/ \ 69 mixart/ \
70 nm256/ \ 70 nm256/ \
71 oxygen/ \
71 pcxhr/ \ 72 pcxhr/ \
72 riptide/ \ 73 riptide/ \
73 rme9652/ \ 74 rme9652/ \
diff --git a/sound/pci/oxygen/Makefile b/sound/pci/oxygen/Makefile
new file mode 100644
index 000000000000..99455dd1576c
--- /dev/null
+++ b/sound/pci/oxygen/Makefile
@@ -0,0 +1,5 @@
1snd-oxygen-lib-objs := oxygen_io.o oxygen_lib.o oxygen_mixer.o oxygen_pcm.o
2snd-oxygen-objs := oxygen.o
3
4obj-$(CONFIG_SND_OXYGEN_LIB) += snd-oxygen-lib.o
5obj-$(CONFIG_SND_OXYGEN) += snd-oxygen.o
diff --git a/sound/pci/oxygen/oxygen.c b/sound/pci/oxygen/oxygen.c
new file mode 100644
index 000000000000..bfef5aba0b9d
--- /dev/null
+++ b/sound/pci/oxygen/oxygen.c
@@ -0,0 +1,314 @@
1/*
2 * C-Media CMI8788 driver for C-Media's reference design and for the X-Meridian
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20/*
21 * SPI 0 -> 1st AK4396 (front)
22 * SPI 1 -> 2nd AK4396 (side)
23 * SPI 2 -> 3rd AK4396 (center/LFE)
24 * SPI 3 -> WM8785
25 * SPI 4 -> 4th AK4396 (rear)
26 *
27 * GPIO 0 -> DFS0 of AK5385
28 * GPIO 1 -> DFS1 of AK5385
29 */
30
31#include <sound/driver.h>
32#include <linux/pci.h>
33#include <sound/core.h>
34#include <sound/initval.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/tlv.h>
38#include "oxygen.h"
39
40MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
41MODULE_DESCRIPTION("C-Media CMI8788 driver");
42MODULE_LICENSE("GPL");
43MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8788}}");
44
45static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
46static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
47static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
48
49module_param_array(index, int, NULL, 0444);
50MODULE_PARM_DESC(index, "card index");
51module_param_array(id, charp, NULL, 0444);
52MODULE_PARM_DESC(id, "ID string");
53module_param_array(enable, bool, NULL, 0444);
54MODULE_PARM_DESC(enable, "enable card");
55
56static struct pci_device_id oxygen_ids[] __devinitdata = {
57 { OXYGEN_PCI_SUBID(0x10b0, 0x0216) },
58 { OXYGEN_PCI_SUBID(0x10b0, 0x0218) },
59 { OXYGEN_PCI_SUBID(0x10b0, 0x0219) },
60 { OXYGEN_PCI_SUBID(0x13f6, 0x0001) },
61 { OXYGEN_PCI_SUBID(0x13f6, 0x0010) },
62 { OXYGEN_PCI_SUBID(0x13f6, 0x8788) },
63 { OXYGEN_PCI_SUBID(0x147a, 0xa017) },
64 { OXYGEN_PCI_SUBID(0x14c3, 0x1710) },
65 { OXYGEN_PCI_SUBID(0x14c3, 0x1711) },
66 { OXYGEN_PCI_SUBID(0x1a58, 0x0910) },
67 { OXYGEN_PCI_SUBID(0x415a, 0x5431), .driver_data = 1 },
68 { OXYGEN_PCI_SUBID(0x7284, 0x9761) },
69 { }
70};
71MODULE_DEVICE_TABLE(pci, oxygen_ids);
72
73#define AK4396_WRITE 0x2000
74
75/* register 0 */
76#define AK4396_RSTN 0x01
77#define AK4396_DIF_24_MSB 0x04
78/* register 1 */
79#define AK4396_SMUTE 0x01
80#define AK4396_DEM_OFF 0x02
81#define AK4396_DFS_MASK 0x18
82#define AK4396_DFS_NORMAL 0x00
83#define AK4396_DFS_DOUBLE 0x08
84#define AK4396_DFS_QUAD 0x10
85
86/* register 0 */
87#define WM8785_OSR_SINGLE 0x000
88#define WM8785_OSR_DOUBLE 0x008
89#define WM8785_OSR_QUAD 0x010
90#define WM8785_FORMAT_LJUST 0x020
91#define WM8785_FORMAT_I2S 0x040
92/* register 1 */
93#define WM8785_WL_16 0x000
94#define WM8785_WL_20 0x001
95#define WM8785_WL_24 0x002
96#define WM8785_WL_32 0x003
97
98static void ak4396_write(struct oxygen *chip, unsigned int codec,
99 u8 reg, u8 value)
100{
101 /* maps ALSA channel pair number to SPI output */
102 static const u8 codec_spi_map[4] = {
103 0, 4, 2, 1
104 };
105 oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER_WRITE |
106 OXYGEN_SPI_DATA_LENGTH_2 |
107 (codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) |
108 OXYGEN_SPI_MAGIC,
109 AK4396_WRITE | (reg << 8) | value);
110}
111
112static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value)
113{
114 oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER_WRITE |
115 OXYGEN_SPI_DATA_LENGTH_2 |
116 (3 << OXYGEN_SPI_CODEC_SHIFT),
117 (reg << 9) | value);
118}
119
120static void ak4396_init(struct oxygen *chip)
121{
122 unsigned int i;
123
124 chip->ak4396_reg1 = AK4396_DEM_OFF | AK4396_DFS_NORMAL;
125 for (i = 0; i < 4; ++i) {
126 ak4396_write(chip, i, 0, AK4396_DIF_24_MSB | AK4396_RSTN);
127 ak4396_write(chip, i, 1, chip->ak4396_reg1);
128 ak4396_write(chip, i, 2, 0);
129 ak4396_write(chip, i, 3, 0xff);
130 ak4396_write(chip, i, 4, 0xff);
131 }
132 snd_component_add(chip->card, "AK4396");
133}
134
135static void ak5385_init(struct oxygen *chip)
136{
137 oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, 0x0003);
138 oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, 0x0003);
139 snd_component_add(chip->card, "AK5385");
140}
141
142static void wm8785_init(struct oxygen *chip)
143{
144 wm8785_write(chip, 7, 0);
145 wm8785_write(chip, 0, WM8785_FORMAT_LJUST | WM8785_OSR_SINGLE);
146 wm8785_write(chip, 1, WM8785_WL_24);
147 snd_component_add(chip->card, "WM8785");
148}
149
150static void generic_init(struct oxygen *chip)
151{
152 ak4396_init(chip);
153 wm8785_init(chip);
154}
155
156static void meridian_init(struct oxygen *chip)
157{
158 ak4396_init(chip);
159 ak5385_init(chip);
160}
161
162static void generic_cleanup(struct oxygen *chip)
163{
164}
165
166static void set_ak4396_params(struct oxygen *chip,
167 struct snd_pcm_hw_params *params)
168{
169 unsigned int i;
170 u8 value;
171
172 value = chip->ak4396_reg1 & ~AK4396_DFS_MASK;
173 if (params_rate(params) <= 54000)
174 value |= AK4396_DFS_NORMAL;
175 else if (params_rate(params) < 120000)
176 value |= AK4396_DFS_DOUBLE;
177 else
178 value |= AK4396_DFS_QUAD;
179 chip->ak4396_reg1 = value;
180 for (i = 0; i < 4; ++i) {
181 ak4396_write(chip, i, 0, AK4396_DIF_24_MSB);
182 ak4396_write(chip, i, 1, value);
183 ak4396_write(chip, i, 0, AK4396_DIF_24_MSB | AK4396_RSTN);
184 }
185}
186
187static void update_ak4396_volume(struct oxygen *chip)
188{
189 unsigned int i;
190
191 for (i = 0; i < 4; ++i) {
192 ak4396_write(chip, i, 3, chip->dac_volume[i * 2]);
193 ak4396_write(chip, i, 4, chip->dac_volume[i * 2 + 1]);
194 }
195}
196
197static void update_ak4396_mute(struct oxygen *chip)
198{
199 unsigned int i;
200 u8 value;
201
202 value = chip->ak4396_reg1 & ~AK4396_SMUTE;
203 if (chip->dac_mute)
204 value |= AK4396_SMUTE;
205 for (i = 0; i < 4; ++i)
206 ak4396_write(chip, i, 1, value);
207}
208
209static void set_wm8785_params(struct oxygen *chip,
210 struct snd_pcm_hw_params *params)
211{
212 unsigned int value;
213
214 wm8785_write(chip, 7, 0);
215
216 value = WM8785_FORMAT_LJUST;
217 if (params_rate(params) == 96000)
218 value |= WM8785_OSR_DOUBLE;
219 else if (params_rate(params) == 192000)
220 value |= WM8785_OSR_QUAD;
221 else
222 value |= WM8785_OSR_SINGLE;
223 wm8785_write(chip, 0, value);
224
225 if (snd_pcm_format_width(params_format(params)) <= 16)
226 value = WM8785_WL_16;
227 else
228 value = WM8785_WL_24;
229 wm8785_write(chip, 1, value);
230}
231
232static void set_ak5385_params(struct oxygen *chip,
233 struct snd_pcm_hw_params *params)
234{
235 unsigned int value;
236
237 if (params_rate(params) <= 54000)
238 value = 0;
239 else if (params_rate(params) <= 108000)
240 value = 1;
241 else
242 value = 2;
243 oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, value, 0x0003);
244}
245
246static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0);
247
248static const struct oxygen_model model_generic = {
249 .shortname = "C-Media CMI8788",
250 .longname = "C-Media Oxygen HD Audio",
251 .chip = "CMI8788",
252 .owner = THIS_MODULE,
253 .init = generic_init,
254 .cleanup = generic_cleanup,
255 .set_dac_params = set_ak4396_params,
256 .set_adc_params = set_wm8785_params,
257 .update_dac_volume = update_ak4396_volume,
258 .update_dac_mute = update_ak4396_mute,
259 .dac_tlv = ak4396_db_scale,
260};
261static const struct oxygen_model model_meridian = {
262 .shortname = "C-Media CMI8788",
263 .longname = "C-Media Oxygen HD Audio",
264 .chip = "CMI8788",
265 .owner = THIS_MODULE,
266 .init = meridian_init,
267 .cleanup = generic_cleanup,
268 .set_dac_params = set_ak4396_params,
269 .set_adc_params = set_ak5385_params,
270 .update_dac_volume = update_ak4396_volume,
271 .update_dac_mute = update_ak4396_mute,
272 .dac_tlv = ak4396_db_scale,
273 .record_from_dma_b = 1,
274};
275
276static int __devinit generic_oxygen_probe(struct pci_dev *pci,
277 const struct pci_device_id *pci_id)
278{
279 static int dev;
280 const struct oxygen_model *model;
281 int err;
282
283 if (dev >= SNDRV_CARDS)
284 return -ENODEV;
285 if (!enable[dev]) {
286 ++dev;
287 return -ENOENT;
288 }
289 model = pci_id->driver_data ? &model_meridian : &model_generic;
290 err = oxygen_pci_probe(pci, index[dev], id[dev], model);
291 if (err >= 0)
292 ++dev;
293 return err;
294}
295
296static struct pci_driver oxygen_driver = {
297 .name = "CMI8788",
298 .id_table = oxygen_ids,
299 .probe = generic_oxygen_probe,
300 .remove = __devexit_p(oxygen_pci_remove),
301};
302
303static int __init alsa_card_oxygen_init(void)
304{
305 return pci_register_driver(&oxygen_driver);
306}
307
308static void __exit alsa_card_oxygen_exit(void)
309{
310 pci_unregister_driver(&oxygen_driver);
311}
312
313module_init(alsa_card_oxygen_init)
314module_exit(alsa_card_oxygen_exit)
diff --git a/sound/pci/oxygen/oxygen.h b/sound/pci/oxygen/oxygen.h
new file mode 100644
index 000000000000..248f7ed22fda
--- /dev/null
+++ b/sound/pci/oxygen/oxygen.h
@@ -0,0 +1,167 @@
1#ifndef OXYGEN_H_INCLUDED
2#define OXYGEN_H_INCLUDED
3
4#include <linux/mutex.h>
5#include <linux/spinlock.h>
6#include <linux/workqueue.h>
7#include "oxygen_regs.h"
8
9/* 1 << PCM_x == OXYGEN_CHANNEL_x */
10#define PCM_A 0
11#define PCM_B 1
12#define PCM_C 2
13#define PCM_SPDIF 3
14#define PCM_MULTICH 4
15#define PCM_AC97 5
16#define PCM_COUNT 6
17
18#define OXYGEN_PCI_SUBID(sv, sd) \
19 .vendor = PCI_VENDOR_ID_CMEDIA, \
20 .device = 0x8788, \
21 .subvendor = sv, \
22 .subdevice = sd
23
24struct pci_dev;
25struct snd_card;
26struct snd_pcm_substream;
27struct snd_pcm_hw_params;
28struct snd_rawmidi;
29struct oxygen_model;
30
31struct oxygen {
32 unsigned long addr;
33 spinlock_t reg_lock;
34 struct mutex mutex;
35 struct snd_card *card;
36 struct pci_dev *pci;
37 struct snd_rawmidi *midi;
38 int irq;
39 const struct oxygen_model *model;
40 unsigned int interrupt_mask;
41 u8 dac_volume[8];
42 u8 dac_mute;
43 u8 pcm_active;
44 u8 pcm_running;
45 u8 dac_routing;
46 u8 spdif_playback_enable;
47 u8 ak4396_reg1;
48 u8 revision;
49 u8 has_2nd_ac97_codec;
50 u32 spdif_bits;
51 u32 spdif_pcm_bits;
52 struct snd_pcm_substream *streams[PCM_COUNT];
53 struct snd_kcontrol *spdif_pcm_ctl;
54 struct snd_kcontrol *spdif_input_bits_ctl;
55 struct work_struct spdif_input_bits_work;
56};
57
58struct oxygen_model {
59 const char *shortname;
60 const char *longname;
61 const char *chip;
62 struct module *owner;
63 void (*init)(struct oxygen *chip);
64 int (*mixer_init)(struct oxygen *chip);
65 void (*cleanup)(struct oxygen *chip);
66 void (*set_dac_params)(struct oxygen *chip,
67 struct snd_pcm_hw_params *params);
68 void (*set_adc_params)(struct oxygen *chip,
69 struct snd_pcm_hw_params *params);
70 void (*update_dac_volume)(struct oxygen *chip);
71 void (*update_dac_mute)(struct oxygen *chip);
72 const unsigned int *dac_tlv;
73 u8 record_from_dma_b;
74 u8 cd_in_from_video_in;
75 u8 dac_minimum_volume;
76};
77
78/* oxygen_lib.c */
79
80int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
81 const struct oxygen_model *model);
82void oxygen_pci_remove(struct pci_dev *pci);
83
84/* oxygen_mixer.c */
85
86int oxygen_mixer_init(struct oxygen *chip);
87void oxygen_update_dac_routing(struct oxygen *chip);
88void oxygen_update_spdif_source(struct oxygen *chip);
89
90/* oxygen_pcm.c */
91
92int oxygen_pcm_init(struct oxygen *chip);
93
94/* oxygen_io.c */
95
96u8 oxygen_read8(struct oxygen *chip, unsigned int reg);
97u16 oxygen_read16(struct oxygen *chip, unsigned int reg);
98u32 oxygen_read32(struct oxygen *chip, unsigned int reg);
99void oxygen_write8(struct oxygen *chip, unsigned int reg, u8 value);
100void oxygen_write16(struct oxygen *chip, unsigned int reg, u16 value);
101void oxygen_write32(struct oxygen *chip, unsigned int reg, u32 value);
102void oxygen_write8_masked(struct oxygen *chip, unsigned int reg,
103 u8 value, u8 mask);
104void oxygen_write16_masked(struct oxygen *chip, unsigned int reg,
105 u16 value, u16 mask);
106void oxygen_write32_masked(struct oxygen *chip, unsigned int reg,
107 u32 value, u32 mask);
108
109u16 oxygen_read_ac97(struct oxygen *chip, unsigned int codec,
110 unsigned int index);
111void oxygen_write_ac97(struct oxygen *chip, unsigned int codec,
112 unsigned int index, u16 data);
113void oxygen_write_ac97_masked(struct oxygen *chip, unsigned int codec,
114 unsigned int index, u16 data, u16 mask);
115
116void oxygen_write_spi(struct oxygen *chip, u8 control, unsigned int data);
117
118static inline void oxygen_set_bits8(struct oxygen *chip,
119 unsigned int reg, u8 value)
120{
121 oxygen_write8_masked(chip, reg, value, value);
122}
123
124static inline void oxygen_set_bits16(struct oxygen *chip,
125 unsigned int reg, u16 value)
126{
127 oxygen_write16_masked(chip, reg, value, value);
128}
129
130static inline void oxygen_set_bits32(struct oxygen *chip,
131 unsigned int reg, u32 value)
132{
133 oxygen_write32_masked(chip, reg, value, value);
134}
135
136static inline void oxygen_clear_bits8(struct oxygen *chip,
137 unsigned int reg, u8 value)
138{
139 oxygen_write8_masked(chip, reg, 0, value);
140}
141
142static inline void oxygen_clear_bits16(struct oxygen *chip,
143 unsigned int reg, u16 value)
144{
145 oxygen_write16_masked(chip, reg, 0, value);
146}
147
148static inline void oxygen_clear_bits32(struct oxygen *chip,
149 unsigned int reg, u32 value)
150{
151 oxygen_write32_masked(chip, reg, 0, value);
152}
153
154static inline void oxygen_ac97_set_bits(struct oxygen *chip, unsigned int codec,
155 unsigned int index, u16 value)
156{
157 oxygen_write_ac97_masked(chip, codec, index, value, value);
158}
159
160static inline void oxygen_ac97_clear_bits(struct oxygen *chip,
161 unsigned int codec,
162 unsigned int index, u16 value)
163{
164 oxygen_write_ac97_masked(chip, codec, index, 0, value);
165}
166
167#endif
diff --git a/sound/pci/oxygen/oxygen_io.c b/sound/pci/oxygen/oxygen_io.c
new file mode 100644
index 000000000000..5f4feeaf8b3a
--- /dev/null
+++ b/sound/pci/oxygen/oxygen_io.c
@@ -0,0 +1,194 @@
1/*
2 * C-Media CMI8788 driver - helper functions
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <sound/driver.h>
21#include <linux/delay.h>
22#include <linux/sched.h>
23#include <sound/core.h>
24#include <asm/io.h>
25#include "oxygen.h"
26
27u8 oxygen_read8(struct oxygen *chip, unsigned int reg)
28{
29 return inb(chip->addr + reg);
30}
31EXPORT_SYMBOL(oxygen_read8);
32
33u16 oxygen_read16(struct oxygen *chip, unsigned int reg)
34{
35 return inw(chip->addr + reg);
36}
37EXPORT_SYMBOL(oxygen_read16);
38
39u32 oxygen_read32(struct oxygen *chip, unsigned int reg)
40{
41 return inl(chip->addr + reg);
42}
43EXPORT_SYMBOL(oxygen_read32);
44
45void oxygen_write8(struct oxygen *chip, unsigned int reg, u8 value)
46{
47 outb(value, chip->addr + reg);
48}
49EXPORT_SYMBOL(oxygen_write8);
50
51void oxygen_write16(struct oxygen *chip, unsigned int reg, u16 value)
52{
53 outw(value, chip->addr + reg);
54}
55EXPORT_SYMBOL(oxygen_write16);
56
57void oxygen_write32(struct oxygen *chip, unsigned int reg, u32 value)
58{
59 outl(value, chip->addr + reg);
60}
61EXPORT_SYMBOL(oxygen_write32);
62
63void oxygen_write8_masked(struct oxygen *chip, unsigned int reg,
64 u8 value, u8 mask)
65{
66 u8 tmp = inb(chip->addr + reg);
67 outb((tmp & ~mask) | (value & mask), chip->addr + reg);
68}
69EXPORT_SYMBOL(oxygen_write8_masked);
70
71void oxygen_write16_masked(struct oxygen *chip, unsigned int reg,
72 u16 value, u16 mask)
73{
74 u16 tmp = inw(chip->addr + reg);
75 outw((tmp & ~mask) | (value & mask), chip->addr + reg);
76}
77EXPORT_SYMBOL(oxygen_write16_masked);
78
79void oxygen_write32_masked(struct oxygen *chip, unsigned int reg,
80 u32 value, u32 mask)
81{
82 u32 tmp = inl(chip->addr + reg);
83 outl((tmp & ~mask) | (value & mask), chip->addr + reg);
84}
85EXPORT_SYMBOL(oxygen_write32_masked);
86
87static int oxygen_ac97_wait(struct oxygen *chip, unsigned int mask)
88{
89 unsigned long timeout = jiffies + msecs_to_jiffies(1);
90 do {
91 udelay(5);
92 cond_resched();
93 if (oxygen_read8(chip, OXYGEN_AC97_INTERRUPT_STATUS) & mask)
94 return 0;
95 } while (time_after_eq(timeout, jiffies));
96 return -EIO;
97}
98
99/*
100 * About 10% of AC'97 register reads or writes fail to complete, but even those
101 * where the controller indicates completion aren't guaranteed to have actually
102 * happened.
103 *
104 * It's hard to assign blame to either the controller or the codec because both
105 * were made by C-Media ...
106 */
107
108void oxygen_write_ac97(struct oxygen *chip, unsigned int codec,
109 unsigned int index, u16 data)
110{
111 unsigned int count, succeeded;
112 u32 reg;
113
114 reg = data;
115 reg |= index << OXYGEN_AC97_REG_ADDR_SHIFT;
116 reg |= OXYGEN_AC97_REG_DIR_WRITE;
117 reg |= codec << OXYGEN_AC97_REG_CODEC_SHIFT;
118 succeeded = 0;
119 for (count = 5; count > 0; --count) {
120 udelay(5);
121 oxygen_write32(chip, OXYGEN_AC97_REGS, reg);
122 /* require two "completed" writes, just to be sure */
123 if (oxygen_ac97_wait(chip, OXYGEN_AC97_WRITE_COMPLETE) >= 0 &&
124 ++succeeded >= 2)
125 return;
126 }
127 snd_printk(KERN_ERR "AC'97 write timeout\n");
128}
129EXPORT_SYMBOL(oxygen_write_ac97);
130
131u16 oxygen_read_ac97(struct oxygen *chip, unsigned int codec,
132 unsigned int index)
133{
134 unsigned int count;
135 unsigned int last_read = UINT_MAX;
136 u32 reg;
137
138 reg = index << OXYGEN_AC97_REG_ADDR_SHIFT;
139 reg |= OXYGEN_AC97_REG_DIR_READ;
140 reg |= codec << OXYGEN_AC97_REG_CODEC_SHIFT;
141 for (count = 5; count > 0; --count) {
142 udelay(5);
143 oxygen_write32(chip, OXYGEN_AC97_REGS, reg);
144 udelay(10);
145 if (oxygen_ac97_wait(chip, OXYGEN_AC97_READ_COMPLETE) >= 0) {
146 u16 value = oxygen_read16(chip, OXYGEN_AC97_REGS);
147 /* we require two consecutive reads of the same value */
148 if (value == last_read)
149 return value;
150 last_read = value;
151 /*
152 * Invert the register value bits to make sure that two
153 * consecutive unsuccessful reads do not return the same
154 * value.
155 */
156 reg ^= 0xffff;
157 }
158 }
159 snd_printk(KERN_ERR "AC'97 read timeout on codec %u\n", codec);
160 return 0;
161}
162EXPORT_SYMBOL(oxygen_read_ac97);
163
164void oxygen_write_ac97_masked(struct oxygen *chip, unsigned int codec,
165 unsigned int index, u16 data, u16 mask)
166{
167 u16 value = oxygen_read_ac97(chip, codec, index);
168 value &= ~mask;
169 value |= data & mask;
170 oxygen_write_ac97(chip, codec, index, value);
171}
172EXPORT_SYMBOL(oxygen_write_ac97_masked);
173
174void oxygen_write_spi(struct oxygen *chip, u8 control, unsigned int data)
175{
176 unsigned int count;
177
178 /* should not need more than 3.84 us (24 * 160 ns) */
179 count = 10;
180 while ((oxygen_read8(chip, OXYGEN_SPI_CONTROL) & OXYGEN_SPI_BUSY)
181 && count > 0) {
182 udelay(1);
183 --count;
184 }
185
186 spin_lock_irq(&chip->reg_lock);
187 oxygen_write8(chip, OXYGEN_SPI_DATA1, data);
188 oxygen_write8(chip, OXYGEN_SPI_DATA2, data >> 8);
189 if (control & OXYGEN_SPI_DATA_LENGTH_3)
190 oxygen_write8(chip, OXYGEN_SPI_DATA3, data >> 16);
191 oxygen_write8(chip, OXYGEN_SPI_CONTROL, control);
192 spin_unlock_irq(&chip->reg_lock);
193}
194EXPORT_SYMBOL(oxygen_write_spi);
diff --git a/sound/pci/oxygen/oxygen_lib.c b/sound/pci/oxygen/oxygen_lib.c
new file mode 100644
index 000000000000..6180cc858e60
--- /dev/null
+++ b/sound/pci/oxygen/oxygen_lib.c
@@ -0,0 +1,361 @@
1/*
2 * C-Media CMI8788 driver - main driver module
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <sound/driver.h>
21#include <linux/delay.h>
22#include <linux/interrupt.h>
23#include <linux/mutex.h>
24#include <linux/pci.h>
25#include <sound/ac97_codec.h>
26#include <sound/asoundef.h>
27#include <sound/core.h>
28#include <sound/info.h>
29#include <sound/mpu401.h>
30#include <sound/pcm.h>
31#include "oxygen.h"
32
33MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
34MODULE_DESCRIPTION("C-Media CMI8788 helper library");
35MODULE_LICENSE("GPL");
36
37
38static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
39{
40 struct oxygen *chip = dev_id;
41 unsigned int status, clear, elapsed_streams, i;
42
43 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
44 if (!status)
45 return IRQ_NONE;
46
47 spin_lock(&chip->reg_lock);
48
49 clear = status & (OXYGEN_CHANNEL_A |
50 OXYGEN_CHANNEL_B |
51 OXYGEN_CHANNEL_C |
52 OXYGEN_CHANNEL_SPDIF |
53 OXYGEN_CHANNEL_MULTICH |
54 OXYGEN_CHANNEL_AC97 |
55 OXYGEN_INT_SPDIF_IN_CHANGE |
56 OXYGEN_INT_GPIO);
57 if (clear) {
58 if (clear & OXYGEN_INT_SPDIF_IN_CHANGE)
59 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_CHANGE;
60 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
61 chip->interrupt_mask & ~clear);
62 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
63 chip->interrupt_mask);
64 }
65
66 elapsed_streams = status & chip->pcm_running;
67
68 spin_unlock(&chip->reg_lock);
69
70 for (i = 0; i < PCM_COUNT; ++i)
71 if ((elapsed_streams & (1 << i)) && chip->streams[i])
72 snd_pcm_period_elapsed(chip->streams[i]);
73
74 if (status & OXYGEN_INT_SPDIF_IN_CHANGE) {
75 spin_lock(&chip->reg_lock);
76 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
77 if (i & OXYGEN_SPDIF_IN_CHANGE) {
78 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
79 schedule_work(&chip->spdif_input_bits_work);
80 }
81 spin_unlock(&chip->reg_lock);
82 }
83
84 if (status & OXYGEN_INT_GPIO)
85 ;
86
87 if ((status & OXYGEN_INT_MIDI) && chip->midi)
88 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
89
90 return IRQ_HANDLED;
91}
92
93static void oxygen_spdif_input_bits_changed(struct work_struct *work)
94{
95 struct oxygen *chip = container_of(work, struct oxygen,
96 spdif_input_bits_work);
97
98 spin_lock_irq(&chip->reg_lock);
99 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_IN_INVERT);
100 spin_unlock_irq(&chip->reg_lock);
101 msleep(1);
102 if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL)
103 & OXYGEN_SPDIF_IN_VALID)) {
104 spin_lock_irq(&chip->reg_lock);
105 oxygen_set_bits32(chip, OXYGEN_SPDIF_CONTROL,
106 OXYGEN_SPDIF_IN_INVERT);
107 spin_unlock_irq(&chip->reg_lock);
108 msleep(1);
109 if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL)
110 & OXYGEN_SPDIF_IN_VALID)) {
111 spin_lock_irq(&chip->reg_lock);
112 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
113 OXYGEN_SPDIF_IN_INVERT);
114 spin_unlock_irq(&chip->reg_lock);
115 }
116 }
117
118 if (chip->spdif_input_bits_ctl) {
119 spin_lock_irq(&chip->reg_lock);
120 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_CHANGE;
121 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
122 chip->interrupt_mask);
123 spin_unlock_irq(&chip->reg_lock);
124
125 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
126 &chip->spdif_input_bits_ctl->id);
127 }
128}
129
130#ifdef CONFIG_PROC_FS
131static void oxygen_proc_read(struct snd_info_entry *entry,
132 struct snd_info_buffer *buffer)
133{
134 struct oxygen *chip = entry->private_data;
135 int i, j;
136
137 snd_iprintf(buffer, "CMI8788\n\n");
138 for (i = 0; i < 0x100; i += 0x10) {
139 snd_iprintf(buffer, "%02x:", i);
140 for (j = 0; j < 0x10; ++j)
141 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
142 snd_iprintf(buffer, "\n");
143 }
144 if (mutex_lock_interruptible(&chip->mutex) < 0)
145 return;
146 snd_iprintf(buffer, "\nAC97\n");
147 for (i = 0; i < 0x80; i += 0x10) {
148 snd_iprintf(buffer, "%02x:", i);
149 for (j = 0; j < 0x10; j += 2)
150 snd_iprintf(buffer, " %04x",
151 oxygen_read_ac97(chip, 0, i + j));
152 snd_iprintf(buffer, "\n");
153 }
154 mutex_unlock(&chip->mutex);
155}
156
157static void __devinit oxygen_proc_init(struct oxygen *chip)
158{
159 struct snd_info_entry *entry;
160
161 if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
162 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
163}
164#else
165#define oxygen_proc_init(chip)
166#endif
167
168static void __devinit oxygen_init(struct oxygen *chip)
169{
170 unsigned int i;
171
172 chip->dac_routing = 1;
173 for (i = 0; i < 8; ++i)
174 chip->dac_volume[i] = 0xff;
175 chip->spdif_playback_enable = 1;
176 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
177 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
178 chip->spdif_pcm_bits = chip->spdif_bits;
179
180 if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
181 chip->revision = 2;
182 else
183 chip->revision = 1;
184
185 if (chip->revision == 1)
186 oxygen_set_bits8(chip, OXYGEN_MISC, OXYGEN_MISC_MAGIC);
187
188 oxygen_set_bits8(chip, OXYGEN_FUNCTION,
189 OXYGEN_FUNCTION_RESET_CODEC |
190 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
191 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT, 0x010a);
192 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, 0x010a);
193 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, 0x010a);
194 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT, 0x010a);
195 oxygen_set_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_MAGIC2);
196 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
197 oxygen_write16(chip, OXYGEN_PLAY_ROUTING, 0x6c00);
198 oxygen_write8(chip, OXYGEN_REC_ROUTING, 0x10);
199 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0x00);
200 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING, 0xe4);
201
202 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
203 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
204
205 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0x00);
206 oxygen_clear_bits16(chip, OXYGEN_AC97_OUT_CONFIG,
207 OXYGEN_AC97_OUT_MAGIC3);
208 oxygen_set_bits16(chip, OXYGEN_AC97_IN_CONFIG,
209 OXYGEN_AC97_IN_MAGIC3);
210 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
211 msleep(1);
212 oxygen_ac97_set_bits(chip, 0, 0x70, 0x0300);
213 oxygen_ac97_set_bits(chip, 0, 0x64, 0x8043);
214 oxygen_ac97_set_bits(chip, 0, 0x62, 0x180f);
215 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
216 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
217 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
218 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
219 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
220 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
221 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
222 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
223 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
224 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
225 oxygen_ac97_clear_bits(chip, 0, 0x72, 0x0001);
226 /* power down unused ADCs and DACs */
227 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
228 AC97_PD_PR0 | AC97_PD_PR1);
229 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
230 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
231}
232
233static void oxygen_card_free(struct snd_card *card)
234{
235 struct oxygen *chip = card->private_data;
236
237 spin_lock_irq(&chip->reg_lock);
238 chip->interrupt_mask = 0;
239 chip->pcm_running = 0;
240 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
241 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
242 spin_unlock_irq(&chip->reg_lock);
243 if (chip->irq >= 0) {
244 free_irq(chip->irq, chip);
245 synchronize_irq(chip->irq);
246 }
247 flush_scheduled_work();
248 chip->model->cleanup(chip);
249 mutex_destroy(&chip->mutex);
250 pci_release_regions(chip->pci);
251 pci_disable_device(chip->pci);
252}
253
254int __devinit oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
255 const struct oxygen_model *model)
256{
257 struct snd_card *card;
258 struct oxygen *chip;
259 int err;
260
261 card = snd_card_new(index, id, model->owner, sizeof *chip);
262 if (!card)
263 return -ENOMEM;
264
265 chip = card->private_data;
266 chip->card = card;
267 chip->pci = pci;
268 chip->irq = -1;
269 chip->model = model;
270 spin_lock_init(&chip->reg_lock);
271 mutex_init(&chip->mutex);
272 INIT_WORK(&chip->spdif_input_bits_work,
273 oxygen_spdif_input_bits_changed);
274
275 err = pci_enable_device(pci);
276 if (err < 0)
277 goto err_card;
278
279 err = pci_request_regions(pci, model->chip);
280 if (err < 0) {
281 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
282 goto err_pci_enable;
283 }
284
285 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
286 pci_resource_len(pci, 0) < 0x100) {
287 snd_printk(KERN_ERR "invalid PCI I/O range\n");
288 err = -ENXIO;
289 goto err_pci_regions;
290 }
291 chip->addr = pci_resource_start(pci, 0);
292
293 pci_set_master(pci);
294 snd_card_set_dev(card, &pci->dev);
295 card->private_free = oxygen_card_free;
296
297 oxygen_init(chip);
298 model->init(chip);
299
300 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
301 model->chip, chip);
302 if (err < 0) {
303 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
304 goto err_card;
305 }
306 chip->irq = pci->irq;
307
308 strcpy(card->driver, model->chip);
309 strcpy(card->shortname, model->shortname);
310 sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
311 model->longname, chip->revision, chip->addr, chip->irq);
312 strcpy(card->mixername, model->chip);
313 snd_component_add(card, model->chip);
314
315 err = oxygen_pcm_init(chip);
316 if (err < 0)
317 goto err_card;
318
319 err = oxygen_mixer_init(chip);
320 if (err < 0)
321 goto err_card;
322
323 if (oxygen_read8(chip, OXYGEN_MISC) & OXYGEN_MISC_MIDI) {
324 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
325 chip->addr + OXYGEN_MPU401,
326 MPU401_INFO_INTEGRATED, 0, 0,
327 &chip->midi);
328 if (err < 0)
329 goto err_card;
330 }
331
332 oxygen_proc_init(chip);
333
334 spin_lock_irq(&chip->reg_lock);
335 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_CHANGE;
336 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
337 spin_unlock_irq(&chip->reg_lock);
338
339 err = snd_card_register(card);
340 if (err < 0)
341 goto err_card;
342
343 pci_set_drvdata(pci, card);
344 return 0;
345
346err_pci_regions:
347 pci_release_regions(pci);
348err_pci_enable:
349 pci_disable_device(pci);
350err_card:
351 snd_card_free(card);
352 return err;
353}
354EXPORT_SYMBOL(oxygen_pci_probe);
355
356void __devexit oxygen_pci_remove(struct pci_dev *pci)
357{
358 snd_card_free(pci_get_drvdata(pci));
359 pci_set_drvdata(pci, NULL);
360}
361EXPORT_SYMBOL(oxygen_pci_remove);
diff --git a/sound/pci/oxygen/oxygen_mixer.c b/sound/pci/oxygen/oxygen_mixer.c
new file mode 100644
index 000000000000..e252abac004e
--- /dev/null
+++ b/sound/pci/oxygen/oxygen_mixer.c
@@ -0,0 +1,623 @@
1/*
2 * C-Media CMI8788 driver - mixer code
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <sound/driver.h>
21#include <linux/mutex.h>
22#include <sound/ac97_codec.h>
23#include <sound/asoundef.h>
24#include <sound/control.h>
25#include <sound/tlv.h>
26#include "oxygen.h"
27
28static int dac_volume_info(struct snd_kcontrol *ctl,
29 struct snd_ctl_elem_info *info)
30{
31 struct oxygen *chip = ctl->private_data;
32
33 info->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
34 info->count = 8;
35 info->value.integer.min = chip->model->dac_minimum_volume;
36 info->value.integer.max = 0xff;
37 return 0;
38}
39
40static int dac_volume_get(struct snd_kcontrol *ctl,
41 struct snd_ctl_elem_value *value)
42{
43 struct oxygen *chip = ctl->private_data;
44 unsigned int i;
45
46 mutex_lock(&chip->mutex);
47 for (i = 0; i < 8; ++i)
48 value->value.integer.value[i] = chip->dac_volume[i];
49 mutex_unlock(&chip->mutex);
50 return 0;
51}
52
53static int dac_volume_put(struct snd_kcontrol *ctl,
54 struct snd_ctl_elem_value *value)
55{
56 struct oxygen *chip = ctl->private_data;
57 unsigned int i;
58 int changed;
59
60 changed = 0;
61 mutex_lock(&chip->mutex);
62 for (i = 0; i < 8; ++i)
63 if (value->value.integer.value[i] != chip->dac_volume[i]) {
64 chip->dac_volume[i] = value->value.integer.value[i];
65 changed = 1;
66 }
67 if (changed)
68 chip->model->update_dac_volume(chip);
69 mutex_unlock(&chip->mutex);
70 return changed;
71}
72
73static int dac_mute_get(struct snd_kcontrol *ctl,
74 struct snd_ctl_elem_value *value)
75{
76 struct oxygen *chip = ctl->private_data;
77
78 mutex_lock(&chip->mutex);
79 value->value.integer.value[0] = !chip->dac_mute;
80 mutex_unlock(&chip->mutex);
81 return 0;
82}
83
84static int dac_mute_put(struct snd_kcontrol *ctl,
85 struct snd_ctl_elem_value *value)
86{
87 struct oxygen *chip = ctl->private_data;
88 int changed;
89
90 mutex_lock(&chip->mutex);
91 changed = !value->value.integer.value[0] != chip->dac_mute;
92 if (changed) {
93 chip->dac_mute = !value->value.integer.value[0];
94 chip->model->update_dac_mute(chip);
95 }
96 mutex_unlock(&chip->mutex);
97 return changed;
98}
99
100static int upmix_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info)
101{
102 static const char *const names[3] = {
103 "Front", "Front+Rear", "Front+Rear+Side"
104 };
105 info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
106 info->count = 1;
107 info->value.enumerated.items = 3;
108 if (info->value.enumerated.item > 2)
109 info->value.enumerated.item = 2;
110 strcpy(info->value.enumerated.name, names[info->value.enumerated.item]);
111 return 0;
112}
113
114static int upmix_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
115{
116 struct oxygen *chip = ctl->private_data;
117
118 mutex_lock(&chip->mutex);
119 value->value.enumerated.item[0] = chip->dac_routing;
120 mutex_unlock(&chip->mutex);
121 return 0;
122}
123
124void oxygen_update_dac_routing(struct oxygen *chip)
125{
126 /*
127 * hardware channel order: front, side, center/lfe, rear
128 * ALSA channel order: front, rear, center/lfe, side
129 */
130 static const unsigned int reg_values[3] = {
131 0x6c00, 0x2c00, 0x2000
132 };
133 unsigned int reg_value;
134
135 if ((oxygen_read8(chip, OXYGEN_PLAY_CHANNELS) &
136 OXYGEN_PLAY_CHANNELS_MASK) == OXYGEN_PLAY_CHANNELS_2)
137 reg_value = reg_values[chip->dac_routing];
138 else
139 reg_value = 0x6c00;
140 oxygen_write16_masked(chip, OXYGEN_PLAY_ROUTING, reg_value, 0xff00);
141}
142
143static int upmix_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
144{
145 struct oxygen *chip = ctl->private_data;
146 int changed;
147
148 mutex_lock(&chip->mutex);
149 changed = value->value.enumerated.item[0] != chip->dac_routing;
150 if (changed) {
151 chip->dac_routing = min(value->value.enumerated.item[0], 2u);
152 spin_lock_irq(&chip->reg_lock);
153 oxygen_update_dac_routing(chip);
154 spin_unlock_irq(&chip->reg_lock);
155 }
156 mutex_unlock(&chip->mutex);
157 return changed;
158}
159
160static int spdif_switch_get(struct snd_kcontrol *ctl,
161 struct snd_ctl_elem_value *value)
162{
163 struct oxygen *chip = ctl->private_data;
164
165 mutex_lock(&chip->mutex);
166 value->value.integer.value[0] = chip->spdif_playback_enable;
167 mutex_unlock(&chip->mutex);
168 return 0;
169}
170
171static unsigned int oxygen_spdif_rate(unsigned int oxygen_rate)
172{
173 switch (oxygen_rate) {
174 case OXYGEN_RATE_32000:
175 return IEC958_AES3_CON_FS_32000 << OXYGEN_SPDIF_CS_RATE_SHIFT;
176 case OXYGEN_RATE_44100:
177 return IEC958_AES3_CON_FS_44100 << OXYGEN_SPDIF_CS_RATE_SHIFT;
178 default: /* OXYGEN_RATE_48000 */
179 return IEC958_AES3_CON_FS_48000 << OXYGEN_SPDIF_CS_RATE_SHIFT;
180 case OXYGEN_RATE_64000:
181 return 0xb << OXYGEN_SPDIF_CS_RATE_SHIFT;
182 case OXYGEN_RATE_88200:
183 return 0x8 << OXYGEN_SPDIF_CS_RATE_SHIFT;
184 case OXYGEN_RATE_96000:
185 return 0xa << OXYGEN_SPDIF_CS_RATE_SHIFT;
186 case OXYGEN_RATE_176400:
187 return 0xc << OXYGEN_SPDIF_CS_RATE_SHIFT;
188 case OXYGEN_RATE_192000:
189 return 0xe << OXYGEN_SPDIF_CS_RATE_SHIFT;
190 }
191}
192
193void oxygen_update_spdif_source(struct oxygen *chip)
194{
195 u32 old_control, new_control;
196 u16 old_routing, new_routing;
197 unsigned int oxygen_rate;
198
199 old_control = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
200 old_routing = oxygen_read16(chip, OXYGEN_PLAY_ROUTING);
201 if (chip->pcm_active & (1 << PCM_SPDIF)) {
202 new_control = old_control | OXYGEN_SPDIF_OUT_ENABLE;
203 new_routing = (old_routing & ~0x00e0) | 0x0000;
204 oxygen_rate = (old_control >> OXYGEN_SPDIF_OUT_RATE_SHIFT)
205 & OXYGEN_I2S_RATE_MASK;
206 /* S/PDIF rate was already set by the caller */
207 } else if ((chip->pcm_active & (1 << PCM_MULTICH)) &&
208 chip->spdif_playback_enable) {
209 new_routing = (old_routing & ~0x00e0) | 0x0020;
210 oxygen_rate = oxygen_read16(chip, OXYGEN_I2S_MULTICH_FORMAT)
211 & OXYGEN_I2S_RATE_MASK;
212 new_control = (old_control & ~OXYGEN_SPDIF_OUT_RATE_MASK) |
213 (oxygen_rate << OXYGEN_SPDIF_OUT_RATE_SHIFT) |
214 OXYGEN_SPDIF_OUT_ENABLE;
215 } else {
216 new_control = old_control & ~OXYGEN_SPDIF_OUT_ENABLE;
217 new_routing = old_routing;
218 oxygen_rate = OXYGEN_RATE_44100;
219 }
220 if (old_routing != new_routing) {
221 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL,
222 new_control & ~OXYGEN_SPDIF_OUT_ENABLE);
223 oxygen_write16(chip, OXYGEN_PLAY_ROUTING, new_routing);
224 }
225 if (new_control & OXYGEN_SPDIF_OUT_ENABLE)
226 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS,
227 oxygen_spdif_rate(oxygen_rate) |
228 ((chip->pcm_active & (1 << PCM_SPDIF)) ?
229 chip->spdif_pcm_bits : chip->spdif_bits));
230 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, new_control);
231}
232
233static int spdif_switch_put(struct snd_kcontrol *ctl,
234 struct snd_ctl_elem_value *value)
235{
236 struct oxygen *chip = ctl->private_data;
237 int changed;
238
239 mutex_lock(&chip->mutex);
240 changed = value->value.integer.value[0] != chip->spdif_playback_enable;
241 if (changed) {
242 chip->spdif_playback_enable = !!value->value.integer.value[0];
243 spin_lock_irq(&chip->reg_lock);
244 oxygen_update_spdif_source(chip);
245 spin_unlock_irq(&chip->reg_lock);
246 }
247 mutex_unlock(&chip->mutex);
248 return changed;
249}
250
251static int spdif_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info)
252{
253 info->type = SNDRV_CTL_ELEM_TYPE_IEC958;
254 info->count = 1;
255 return 0;
256}
257
258static void oxygen_to_iec958(u32 bits, struct snd_ctl_elem_value *value)
259{
260 value->value.iec958.status[0] =
261 bits & (OXYGEN_SPDIF_NONAUDIO | OXYGEN_SPDIF_C |
262 OXYGEN_SPDIF_PREEMPHASIS);
263 value->value.iec958.status[1] = /* category and original */
264 bits >> OXYGEN_SPDIF_CATEGORY_SHIFT;
265}
266
267static u32 iec958_to_oxygen(struct snd_ctl_elem_value *value)
268{
269 u32 bits;
270
271 bits = value->value.iec958.status[0] &
272 (OXYGEN_SPDIF_NONAUDIO | OXYGEN_SPDIF_C |
273 OXYGEN_SPDIF_PREEMPHASIS);
274 bits |= value->value.iec958.status[1] << OXYGEN_SPDIF_CATEGORY_SHIFT;
275 if (bits & OXYGEN_SPDIF_NONAUDIO)
276 bits |= OXYGEN_SPDIF_V;
277 return bits;
278}
279
280static inline void write_spdif_bits(struct oxygen *chip, u32 bits)
281{
282 oxygen_write32_masked(chip, OXYGEN_SPDIF_OUTPUT_BITS, bits,
283 OXYGEN_SPDIF_NONAUDIO |
284 OXYGEN_SPDIF_C |
285 OXYGEN_SPDIF_PREEMPHASIS |
286 OXYGEN_SPDIF_CATEGORY_MASK |
287 OXYGEN_SPDIF_ORIGINAL |
288 OXYGEN_SPDIF_V);
289}
290
291static int spdif_default_get(struct snd_kcontrol *ctl,
292 struct snd_ctl_elem_value *value)
293{
294 struct oxygen *chip = ctl->private_data;
295
296 mutex_lock(&chip->mutex);
297 oxygen_to_iec958(chip->spdif_bits, value);
298 mutex_unlock(&chip->mutex);
299 return 0;
300}
301
302static int spdif_default_put(struct snd_kcontrol *ctl,
303 struct snd_ctl_elem_value *value)
304{
305 struct oxygen *chip = ctl->private_data;
306 u32 new_bits;
307 int changed;
308
309 new_bits = iec958_to_oxygen(value);
310 mutex_lock(&chip->mutex);
311 changed = new_bits != chip->spdif_bits;
312 if (changed) {
313 chip->spdif_bits = new_bits;
314 if (!(chip->pcm_active & (1 << PCM_SPDIF)))
315 write_spdif_bits(chip, new_bits);
316 }
317 mutex_unlock(&chip->mutex);
318 return changed;
319}
320
321static int spdif_mask_get(struct snd_kcontrol *ctl,
322 struct snd_ctl_elem_value *value)
323{
324 value->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
325 IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS;
326 value->value.iec958.status[1] =
327 IEC958_AES1_CON_CATEGORY | IEC958_AES1_CON_ORIGINAL;
328 return 0;
329}
330
331static int spdif_pcm_get(struct snd_kcontrol *ctl,
332 struct snd_ctl_elem_value *value)
333{
334 struct oxygen *chip = ctl->private_data;
335
336 mutex_lock(&chip->mutex);
337 oxygen_to_iec958(chip->spdif_pcm_bits, value);
338 mutex_unlock(&chip->mutex);
339 return 0;
340}
341
342static int spdif_pcm_put(struct snd_kcontrol *ctl,
343 struct snd_ctl_elem_value *value)
344{
345 struct oxygen *chip = ctl->private_data;
346 u32 new_bits;
347 int changed;
348
349 new_bits = iec958_to_oxygen(value);
350 mutex_lock(&chip->mutex);
351 changed = new_bits != chip->spdif_pcm_bits;
352 if (changed) {
353 chip->spdif_pcm_bits = new_bits;
354 if (chip->pcm_active & (1 << PCM_SPDIF))
355 write_spdif_bits(chip, new_bits);
356 }
357 mutex_unlock(&chip->mutex);
358 return changed;
359}
360
361static int spdif_input_mask_get(struct snd_kcontrol *ctl,
362 struct snd_ctl_elem_value *value)
363{
364 value->value.iec958.status[0] = 0xff;
365 value->value.iec958.status[1] = 0xff;
366 value->value.iec958.status[2] = 0xff;
367 value->value.iec958.status[3] = 0xff;
368 return 0;
369}
370
371static int spdif_input_default_get(struct snd_kcontrol *ctl,
372 struct snd_ctl_elem_value *value)
373{
374 struct oxygen *chip = ctl->private_data;
375 u32 bits;
376
377 bits = oxygen_read32(chip, OXYGEN_SPDIF_INPUT_BITS);
378 value->value.iec958.status[0] = bits;
379 value->value.iec958.status[1] = bits >> 8;
380 value->value.iec958.status[2] = bits >> 16;
381 value->value.iec958.status[3] = bits >> 24;
382 return 0;
383}
384
385static int ac97_switch_get(struct snd_kcontrol *ctl,
386 struct snd_ctl_elem_value *value)
387{
388 struct oxygen *chip = ctl->private_data;
389 unsigned int index = ctl->private_value & 0xff;
390 unsigned int bitnr = (ctl->private_value >> 8) & 0xff;
391 int invert = ctl->private_value & (1 << 16);
392 u16 reg;
393
394 mutex_lock(&chip->mutex);
395 reg = oxygen_read_ac97(chip, 0, index);
396 mutex_unlock(&chip->mutex);
397 if (!(reg & (1 << bitnr)) ^ !invert)
398 value->value.integer.value[0] = 1;
399 else
400 value->value.integer.value[0] = 0;
401 return 0;
402}
403
404static int ac97_switch_put(struct snd_kcontrol *ctl,
405 struct snd_ctl_elem_value *value)
406{
407 struct oxygen *chip = ctl->private_data;
408 unsigned int index = ctl->private_value & 0xff;
409 unsigned int bitnr = (ctl->private_value >> 8) & 0xff;
410 int invert = ctl->private_value & (1 << 16);
411 u16 oldreg, newreg;
412 int change;
413
414 mutex_lock(&chip->mutex);
415 oldreg = oxygen_read_ac97(chip, 0, index);
416 newreg = oldreg;
417 if (!value->value.integer.value[0] ^ !invert)
418 newreg |= 1 << bitnr;
419 else
420 newreg &= ~(1 << bitnr);
421 change = newreg != oldreg;
422 if (change) {
423 oxygen_write_ac97(chip, 0, index, newreg);
424 if (index == AC97_LINE)
425 oxygen_write_ac97_masked(chip, 0, 0x72,
426 !!(newreg & 0x8000), 0x0001);
427 }
428 mutex_unlock(&chip->mutex);
429 return change;
430}
431
432static int ac97_volume_info(struct snd_kcontrol *ctl,
433 struct snd_ctl_elem_info *info)
434{
435 info->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
436 info->count = 2;
437 info->value.integer.min = 0;
438 info->value.integer.max = 0x1f;
439 return 0;
440}
441
442static int ac97_volume_get(struct snd_kcontrol *ctl,
443 struct snd_ctl_elem_value *value)
444{
445 struct oxygen *chip = ctl->private_data;
446 unsigned int index = ctl->private_value;
447 u16 reg;
448
449 mutex_lock(&chip->mutex);
450 reg = oxygen_read_ac97(chip, 0, index);
451 mutex_unlock(&chip->mutex);
452 value->value.integer.value[0] = 31 - (reg & 0x1f);
453 value->value.integer.value[1] = 31 - ((reg >> 8) & 0x1f);
454 return 0;
455}
456
457static int ac97_volume_put(struct snd_kcontrol *ctl,
458 struct snd_ctl_elem_value *value)
459{
460 struct oxygen *chip = ctl->private_data;
461 unsigned int index = ctl->private_value;
462 u16 oldreg, newreg;
463 int change;
464
465 mutex_lock(&chip->mutex);
466 oldreg = oxygen_read_ac97(chip, 0, index);
467 newreg = oldreg;
468 newreg = (newreg & ~0x1f) |
469 (31 - (value->value.integer.value[0] & 0x1f));
470 newreg = (newreg & ~0x1f00) |
471 ((31 - (value->value.integer.value[0] & 0x1f)) << 8);
472 change = newreg != oldreg;
473 if (change)
474 oxygen_write_ac97(chip, 0, index, newreg);
475 mutex_unlock(&chip->mutex);
476 return change;
477}
478
479#define AC97_SWITCH(xname, index, bitnr, invert) { \
480 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
481 .name = xname, \
482 .info = snd_ctl_boolean_mono_info, \
483 .get = ac97_switch_get, \
484 .put = ac97_switch_put, \
485 .private_value = ((invert) << 16) | ((bitnr) << 8) | (index), \
486 }
487#define AC97_VOLUME(xname, index) { \
488 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
489 .name = xname, \
490 .info = ac97_volume_info, \
491 .get = ac97_volume_get, \
492 .put = ac97_volume_put, \
493 .tlv = { .p = ac97_db_scale, }, \
494 .private_value = (index), \
495 }
496
497static DECLARE_TLV_DB_SCALE(ac97_db_scale, -3450, 150, 0);
498
499static const struct snd_kcontrol_new controls[] = {
500 {
501 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
502 .name = "PCM Playback Volume",
503 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
504 SNDRV_CTL_ELEM_ACCESS_TLV_READ,
505 .info = dac_volume_info,
506 .get = dac_volume_get,
507 .put = dac_volume_put,
508 .tlv = {
509 .p = NULL, /* set later */
510 },
511 },
512 {
513 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
514 .name = "PCM Playback Switch",
515 .info = snd_ctl_boolean_mono_info,
516 .get = dac_mute_get,
517 .put = dac_mute_put,
518 },
519 {
520 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
521 .name = "Stereo Upmixing",
522 .info = upmix_info,
523 .get = upmix_get,
524 .put = upmix_put,
525 },
526 {
527 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
528 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH),
529 .info = snd_ctl_boolean_mono_info,
530 .get = spdif_switch_get,
531 .put = spdif_switch_put,
532 },
533 {
534 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
535 .device = 1,
536 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
537 .info = spdif_info,
538 .get = spdif_default_get,
539 .put = spdif_default_put,
540 },
541 {
542 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
543 .device = 1,
544 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
545 .access = SNDRV_CTL_ELEM_ACCESS_READ,
546 .info = spdif_info,
547 .get = spdif_mask_get,
548 },
549 {
550 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
551 .device = 1,
552 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
553 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
554 SNDRV_CTL_ELEM_ACCESS_INACTIVE,
555 .info = spdif_info,
556 .get = spdif_pcm_get,
557 .put = spdif_pcm_put,
558 },
559 {
560 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
561 .device = 1,
562 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK),
563 .access = SNDRV_CTL_ELEM_ACCESS_READ,
564 .info = spdif_info,
565 .get = spdif_input_mask_get,
566 },
567 {
568 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
569 .device = 1,
570 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
571 .access = SNDRV_CTL_ELEM_ACCESS_READ,
572 .info = spdif_info,
573 .get = spdif_input_default_get,
574 },
575 AC97_VOLUME("Mic Capture Volume", AC97_MIC),
576 AC97_SWITCH("Mic Capture Switch", AC97_MIC, 15, 1),
577 AC97_SWITCH("Mic Boost (+20dB)", AC97_MIC, 6, 0),
578 AC97_SWITCH("Line Capture Switch", AC97_LINE, 15, 1),
579 AC97_VOLUME("CD Capture Volume", AC97_CD),
580 AC97_SWITCH("CD Capture Switch", AC97_CD, 15, 1),
581 AC97_VOLUME("Aux Capture Volume", AC97_AUX),
582 AC97_SWITCH("Aux Capture Switch", AC97_AUX, 15, 1),
583};
584
585static void oxygen_any_ctl_free(struct snd_kcontrol *ctl)
586{
587 struct oxygen *chip = ctl->private_data;
588
589 /* I'm too lazy to write a function for each control :-) */
590 chip->spdif_pcm_ctl = NULL;
591 chip->spdif_input_bits_ctl = NULL;
592}
593
594int oxygen_mixer_init(struct oxygen *chip)
595{
596 unsigned int i;
597 struct snd_kcontrol *ctl;
598 int err;
599
600 for (i = 0; i < ARRAY_SIZE(controls); ++i) {
601 ctl = snd_ctl_new1(&controls[i], chip);
602 if (!ctl)
603 return -ENOMEM;
604 if (!strcmp(ctl->id.name, "PCM Playback Volume"))
605 ctl->tlv.p = chip->model->dac_tlv;
606 else if (chip->model->cd_in_from_video_in &&
607 !strncmp(ctl->id.name, "CD Capture ", 11))
608 ctl->private_value ^= AC97_CD ^ AC97_VIDEO;
609 err = snd_ctl_add(chip->card, ctl);
610 if (err < 0)
611 return err;
612 if (!strcmp(ctl->id.name,
613 SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM))) {
614 chip->spdif_pcm_ctl = ctl;
615 ctl->private_free = oxygen_any_ctl_free;
616 } else if (!strcmp(ctl->id.name,
617 SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT))) {
618 chip->spdif_input_bits_ctl = ctl;
619 ctl->private_free = oxygen_any_ctl_free;
620 }
621 }
622 return chip->model->mixer_init ? chip->model->mixer_init(chip) : 0;
623}
diff --git a/sound/pci/oxygen/oxygen_pcm.c b/sound/pci/oxygen/oxygen_pcm.c
new file mode 100644
index 000000000000..941399bcab8a
--- /dev/null
+++ b/sound/pci/oxygen/oxygen_pcm.c
@@ -0,0 +1,726 @@
1/*
2 * C-Media CMI8788 driver - PCM code
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <sound/driver.h>
21#include <linux/pci.h>
22#include <sound/control.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include "oxygen.h"
27
28static struct snd_pcm_hardware oxygen_hardware[PCM_COUNT] = {
29 [PCM_A] = {
30 .info = SNDRV_PCM_INFO_MMAP |
31 SNDRV_PCM_INFO_MMAP_VALID |
32 SNDRV_PCM_INFO_INTERLEAVED |
33 SNDRV_PCM_INFO_PAUSE |
34 SNDRV_PCM_INFO_SYNC_START,
35 .formats = SNDRV_PCM_FMTBIT_S16_LE |
36 SNDRV_PCM_FMTBIT_S32_LE,
37 .rates = SNDRV_PCM_RATE_44100 |
38 SNDRV_PCM_RATE_48000 |
39 SNDRV_PCM_RATE_96000 |
40 SNDRV_PCM_RATE_192000,
41 .rate_min = 44100,
42 .rate_max = 192000,
43 .channels_min = 2,
44 .channels_max = 2,
45 .buffer_bytes_max = 256 * 1024,
46 .period_bytes_min = 128,
47 .period_bytes_max = 128 * 1024,
48 .periods_min = 2,
49 .periods_max = 2048,
50 },
51 [PCM_B] = {
52 .info = SNDRV_PCM_INFO_MMAP |
53 SNDRV_PCM_INFO_MMAP_VALID |
54 SNDRV_PCM_INFO_INTERLEAVED |
55 SNDRV_PCM_INFO_PAUSE |
56 SNDRV_PCM_INFO_SYNC_START,
57 .formats = SNDRV_PCM_FMTBIT_S16_LE |
58 SNDRV_PCM_FMTBIT_S32_LE,
59 .rates = SNDRV_PCM_RATE_32000 |
60 SNDRV_PCM_RATE_44100 |
61 SNDRV_PCM_RATE_48000 |
62 SNDRV_PCM_RATE_64000 |
63 SNDRV_PCM_RATE_88200 |
64 SNDRV_PCM_RATE_96000 |
65 SNDRV_PCM_RATE_176400 |
66 SNDRV_PCM_RATE_192000,
67 .rate_min = 32000,
68 .rate_max = 192000,
69 .channels_min = 2,
70 .channels_max = 2,
71 .buffer_bytes_max = 256 * 1024,
72 .period_bytes_min = 128,
73 .period_bytes_max = 128 * 1024,
74 .periods_min = 2,
75 .periods_max = 2048,
76 },
77 [PCM_C] = {
78 .info = SNDRV_PCM_INFO_MMAP |
79 SNDRV_PCM_INFO_MMAP_VALID |
80 SNDRV_PCM_INFO_INTERLEAVED |
81 SNDRV_PCM_INFO_PAUSE |
82 SNDRV_PCM_INFO_SYNC_START,
83 .formats = SNDRV_PCM_FMTBIT_S16_LE |
84 SNDRV_PCM_FMTBIT_S32_LE,
85 .rates = SNDRV_PCM_RATE_44100 |
86 SNDRV_PCM_RATE_48000 |
87 SNDRV_PCM_RATE_88200 |
88 SNDRV_PCM_RATE_96000,
89 .rate_min = 44100,
90 .rate_max = 96000,
91 .channels_min = 2,
92 .channels_max = 2,
93 .buffer_bytes_max = 256 * 1024,
94 .period_bytes_min = 128,
95 .period_bytes_max = 128 * 1024,
96 .periods_min = 2,
97 .periods_max = 2048,
98 },
99 [PCM_SPDIF] = {
100 .info = SNDRV_PCM_INFO_MMAP |
101 SNDRV_PCM_INFO_MMAP_VALID |
102 SNDRV_PCM_INFO_INTERLEAVED |
103 SNDRV_PCM_INFO_PAUSE |
104 SNDRV_PCM_INFO_SYNC_START,
105 .formats = SNDRV_PCM_FMTBIT_S16_LE |
106 SNDRV_PCM_FMTBIT_S32_LE,
107 .rates = SNDRV_PCM_RATE_32000 |
108 SNDRV_PCM_RATE_44100 |
109 SNDRV_PCM_RATE_48000 |
110 SNDRV_PCM_RATE_64000 |
111 SNDRV_PCM_RATE_88200 |
112 SNDRV_PCM_RATE_96000 |
113 SNDRV_PCM_RATE_176400 |
114 SNDRV_PCM_RATE_192000,
115 .rate_min = 32000,
116 .rate_max = 192000,
117 .channels_min = 2,
118 .channels_max = 2,
119 .buffer_bytes_max = 256 * 1024,
120 .period_bytes_min = 128,
121 .period_bytes_max = 128 * 1024,
122 .periods_min = 2,
123 .periods_max = 2048,
124 },
125 [PCM_MULTICH] = {
126 .info = SNDRV_PCM_INFO_MMAP |
127 SNDRV_PCM_INFO_MMAP_VALID |
128 SNDRV_PCM_INFO_INTERLEAVED |
129 SNDRV_PCM_INFO_PAUSE |
130 SNDRV_PCM_INFO_SYNC_START,
131 .formats = SNDRV_PCM_FMTBIT_S16_LE |
132 SNDRV_PCM_FMTBIT_S32_LE,
133 .rates = SNDRV_PCM_RATE_32000 |
134 SNDRV_PCM_RATE_44100 |
135 SNDRV_PCM_RATE_48000 |
136 SNDRV_PCM_RATE_64000 |
137 SNDRV_PCM_RATE_88200 |
138 SNDRV_PCM_RATE_96000 |
139 SNDRV_PCM_RATE_176400 |
140 SNDRV_PCM_RATE_192000,
141 .rate_min = 32000,
142 .rate_max = 192000,
143 .channels_min = 2,
144 .channels_max = 8,
145 .buffer_bytes_max = 2048 * 1024,
146 .period_bytes_min = 128,
147 .period_bytes_max = 256 * 1024,
148 .periods_min = 2,
149 .periods_max = 16384,
150 },
151 [PCM_AC97] = {
152 .info = SNDRV_PCM_INFO_MMAP |
153 SNDRV_PCM_INFO_MMAP_VALID |
154 SNDRV_PCM_INFO_INTERLEAVED |
155 SNDRV_PCM_INFO_PAUSE |
156 SNDRV_PCM_INFO_SYNC_START,
157 .formats = SNDRV_PCM_FMTBIT_S16_LE,
158 .rates = SNDRV_PCM_RATE_48000,
159 .rate_min = 48000,
160 .rate_max = 48000,
161 .channels_min = 2,
162 .channels_max = 2,
163 .buffer_bytes_max = 256 * 1024,
164 .period_bytes_min = 128,
165 .period_bytes_max = 128 * 1024,
166 .periods_min = 2,
167 .periods_max = 2048,
168 },
169};
170
171static int oxygen_open(struct snd_pcm_substream *substream,
172 unsigned int channel)
173{
174 struct oxygen *chip = snd_pcm_substream_chip(substream);
175 struct snd_pcm_runtime *runtime = substream->runtime;
176 int err;
177
178 runtime->private_data = (void *)channel;
179 runtime->hw = oxygen_hardware[channel];
180 err = snd_pcm_hw_constraint_step(runtime, 0,
181 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
182 if (err < 0)
183 return err;
184 err = snd_pcm_hw_constraint_step(runtime, 0,
185 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
186 if (err < 0)
187 return err;
188 if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
189 err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
190 if (err < 0)
191 return err;
192 }
193 if (runtime->hw.channels_max > 2) {
194 err = snd_pcm_hw_constraint_step(runtime, 0,
195 SNDRV_PCM_HW_PARAM_CHANNELS,
196 2);
197 if (err < 0)
198 return err;
199 }
200 snd_pcm_set_sync(substream);
201 chip->streams[channel] = substream;
202
203 mutex_lock(&chip->mutex);
204 chip->pcm_active |= 1 << channel;
205 if (channel == PCM_SPDIF) {
206 chip->spdif_pcm_bits = chip->spdif_bits;
207 chip->spdif_pcm_ctl->vd[0].access &=
208 ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
209 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
210 SNDRV_CTL_EVENT_MASK_INFO,
211 &chip->spdif_pcm_ctl->id);
212 }
213 mutex_unlock(&chip->mutex);
214
215 return 0;
216}
217
218static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
219{
220 return oxygen_open(substream, PCM_A);
221}
222
223static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
224{
225 return oxygen_open(substream, PCM_B);
226}
227
228static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
229{
230 return oxygen_open(substream, PCM_C);
231}
232
233static int oxygen_spdif_open(struct snd_pcm_substream *substream)
234{
235 return oxygen_open(substream, PCM_SPDIF);
236}
237
238static int oxygen_multich_open(struct snd_pcm_substream *substream)
239{
240 return oxygen_open(substream, PCM_MULTICH);
241}
242
243static int oxygen_ac97_open(struct snd_pcm_substream *substream)
244{
245 return oxygen_open(substream, PCM_AC97);
246}
247
248static int oxygen_close(struct snd_pcm_substream *substream)
249{
250 struct oxygen *chip = snd_pcm_substream_chip(substream);
251 unsigned int channel = (unsigned int)substream->runtime->private_data;
252
253 mutex_lock(&chip->mutex);
254 chip->pcm_active &= ~(1 << channel);
255 if (channel == PCM_SPDIF) {
256 chip->spdif_pcm_ctl->vd[0].access |=
257 SNDRV_CTL_ELEM_ACCESS_INACTIVE;
258 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
259 SNDRV_CTL_EVENT_MASK_INFO,
260 &chip->spdif_pcm_ctl->id);
261 }
262 if (channel == PCM_SPDIF || channel == PCM_MULTICH)
263 oxygen_update_spdif_source(chip);
264 mutex_unlock(&chip->mutex);
265
266 chip->streams[channel] = NULL;
267 return 0;
268}
269
270static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
271{
272 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
273 return OXYGEN_FORMAT_24;
274 else
275 return OXYGEN_FORMAT_16;
276}
277
278static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
279{
280 switch (params_rate(hw_params)) {
281 case 32000:
282 return OXYGEN_RATE_32000;
283 case 44100:
284 return OXYGEN_RATE_44100;
285 default: /* 48000 */
286 return OXYGEN_RATE_48000;
287 case 64000:
288 return OXYGEN_RATE_64000;
289 case 88200:
290 return OXYGEN_RATE_88200;
291 case 96000:
292 return OXYGEN_RATE_96000;
293 case 176400:
294 return OXYGEN_RATE_176400;
295 case 192000:
296 return OXYGEN_RATE_192000;
297 }
298}
299
300static unsigned int oxygen_i2s_magic2(struct snd_pcm_hw_params *hw_params)
301{
302 return params_rate(hw_params) <= 96000 ? 0x10 : 0x00;
303}
304
305static unsigned int oxygen_i2s_format(struct snd_pcm_hw_params *hw_params)
306{
307 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
308 return OXYGEN_I2S_FORMAT_24;
309 else
310 return OXYGEN_I2S_FORMAT_16;
311}
312
313static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
314{
315 switch (params_channels(hw_params)) {
316 default: /* 2 */
317 return OXYGEN_PLAY_CHANNELS_2;
318 case 4:
319 return OXYGEN_PLAY_CHANNELS_4;
320 case 6:
321 return OXYGEN_PLAY_CHANNELS_6;
322 case 8:
323 return OXYGEN_PLAY_CHANNELS_8;
324 }
325}
326
327static const unsigned int channel_base_registers[PCM_COUNT] = {
328 [PCM_A] = OXYGEN_DMA_A_ADDRESS,
329 [PCM_B] = OXYGEN_DMA_B_ADDRESS,
330 [PCM_C] = OXYGEN_DMA_C_ADDRESS,
331 [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
332 [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
333 [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
334};
335
336static int oxygen_hw_params(struct snd_pcm_substream *substream,
337 struct snd_pcm_hw_params *hw_params)
338{
339 struct oxygen *chip = snd_pcm_substream_chip(substream);
340 unsigned int channel = (unsigned int)substream->runtime->private_data;
341 int err;
342
343 err = snd_pcm_lib_malloc_pages(substream,
344 params_buffer_bytes(hw_params));
345 if (err < 0)
346 return err;
347
348 oxygen_write32(chip, channel_base_registers[channel],
349 (u32)substream->runtime->dma_addr);
350 if (channel == PCM_MULTICH) {
351 oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
352 params_buffer_bytes(hw_params) / 4 - 1);
353 oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
354 params_period_bytes(hw_params) / 4 - 1);
355 } else {
356 oxygen_write16(chip, channel_base_registers[channel] + 4,
357 params_buffer_bytes(hw_params) / 4 - 1);
358 oxygen_write16(chip, channel_base_registers[channel] + 6,
359 params_period_bytes(hw_params) / 4 - 1);
360 }
361 return 0;
362}
363
364static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
365 struct snd_pcm_hw_params *hw_params)
366{
367 struct oxygen *chip = snd_pcm_substream_chip(substream);
368 int err;
369
370 err = oxygen_hw_params(substream, hw_params);
371 if (err < 0)
372 return err;
373
374 spin_lock_irq(&chip->reg_lock);
375 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
376 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
377 OXYGEN_REC_FORMAT_A_MASK);
378 oxygen_write8_masked(chip, OXYGEN_I2S_A_FORMAT,
379 oxygen_rate(hw_params) |
380 oxygen_i2s_magic2(hw_params) |
381 oxygen_i2s_format(hw_params),
382 OXYGEN_I2S_RATE_MASK |
383 OXYGEN_I2S_MAGIC2_MASK |
384 OXYGEN_I2S_FORMAT_MASK);
385 oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x08);
386 spin_unlock_irq(&chip->reg_lock);
387
388 mutex_lock(&chip->mutex);
389 chip->model->set_adc_params(chip, hw_params);
390 mutex_unlock(&chip->mutex);
391 return 0;
392}
393
394static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
395 struct snd_pcm_hw_params *hw_params)
396{
397 struct oxygen *chip = snd_pcm_substream_chip(substream);
398 int err;
399
400 err = oxygen_hw_params(substream, hw_params);
401 if (err < 0)
402 return err;
403
404 spin_lock_irq(&chip->reg_lock);
405 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
406 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
407 OXYGEN_REC_FORMAT_B_MASK);
408 oxygen_write8_masked(chip, OXYGEN_I2S_B_FORMAT,
409 oxygen_rate(hw_params) |
410 oxygen_i2s_magic2(hw_params) |
411 oxygen_i2s_format(hw_params),
412 OXYGEN_I2S_RATE_MASK |
413 OXYGEN_I2S_MAGIC2_MASK |
414 OXYGEN_I2S_FORMAT_MASK);
415 oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x10);
416 spin_unlock_irq(&chip->reg_lock);
417
418 mutex_lock(&chip->mutex);
419 chip->model->set_adc_params(chip, hw_params);
420 mutex_unlock(&chip->mutex);
421 return 0;
422}
423
424static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
425 struct snd_pcm_hw_params *hw_params)
426{
427 struct oxygen *chip = snd_pcm_substream_chip(substream);
428 int err;
429
430 err = oxygen_hw_params(substream, hw_params);
431 if (err < 0)
432 return err;
433
434 spin_lock_irq(&chip->reg_lock);
435 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
436 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
437 OXYGEN_REC_FORMAT_C_MASK);
438 oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x20);
439 spin_unlock_irq(&chip->reg_lock);
440 return 0;
441}
442
443static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
444 struct snd_pcm_hw_params *hw_params)
445{
446 struct oxygen *chip = snd_pcm_substream_chip(substream);
447 int err;
448
449 err = oxygen_hw_params(substream, hw_params);
450 if (err < 0)
451 return err;
452
453 spin_lock_irq(&chip->reg_lock);
454 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
455 OXYGEN_SPDIF_OUT_ENABLE);
456 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
457 oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
458 OXYGEN_SPDIF_FORMAT_MASK);
459 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
460 oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
461 OXYGEN_SPDIF_OUT_RATE_MASK);
462 oxygen_update_spdif_source(chip);
463 spin_unlock_irq(&chip->reg_lock);
464 return 0;
465}
466
467static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
468 struct snd_pcm_hw_params *hw_params)
469{
470 struct oxygen *chip = snd_pcm_substream_chip(substream);
471 int err;
472
473 err = oxygen_hw_params(substream, hw_params);
474 if (err < 0)
475 return err;
476
477 spin_lock_irq(&chip->reg_lock);
478 oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
479 oxygen_play_channels(hw_params),
480 OXYGEN_PLAY_CHANNELS_MASK);
481 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
482 oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
483 OXYGEN_MULTICH_FORMAT_MASK);
484 oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
485 oxygen_rate(hw_params) | oxygen_i2s_format(hw_params),
486 OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_FORMAT_MASK);
487 oxygen_clear_bits16(chip, OXYGEN_PLAY_ROUTING, 0x001f);
488 oxygen_update_dac_routing(chip);
489 oxygen_update_spdif_source(chip);
490 spin_unlock_irq(&chip->reg_lock);
491
492 mutex_lock(&chip->mutex);
493 chip->model->set_dac_params(chip, hw_params);
494 mutex_unlock(&chip->mutex);
495 return 0;
496}
497
498static int oxygen_ac97_hw_params(struct snd_pcm_substream *substream,
499 struct snd_pcm_hw_params *hw_params)
500{
501 struct oxygen *chip = snd_pcm_substream_chip(substream);
502 int err;
503
504 err = oxygen_hw_params(substream, hw_params);
505 if (err < 0)
506 return err;
507
508 spin_lock_irq(&chip->reg_lock);
509 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
510 oxygen_format(hw_params) << OXYGEN_AC97_FORMAT_SHIFT,
511 OXYGEN_AC97_FORMAT_MASK);
512 spin_unlock_irq(&chip->reg_lock);
513 return 0;
514}
515
516static int oxygen_hw_free(struct snd_pcm_substream *substream)
517{
518 struct oxygen *chip = snd_pcm_substream_chip(substream);
519 unsigned int channel = (unsigned int)substream->runtime->private_data;
520
521 spin_lock_irq(&chip->reg_lock);
522 chip->interrupt_mask &= ~(1 << channel);
523 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
524 spin_unlock_irq(&chip->reg_lock);
525
526 return snd_pcm_lib_free_pages(substream);
527}
528
529static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
530{
531 struct oxygen *chip = snd_pcm_substream_chip(substream);
532
533 spin_lock_irq(&chip->reg_lock);
534 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
535 OXYGEN_SPDIF_OUT_ENABLE);
536 spin_unlock_irq(&chip->reg_lock);
537 return oxygen_hw_free(substream);
538}
539
540static int oxygen_prepare(struct snd_pcm_substream *substream)
541{
542 struct oxygen *chip = snd_pcm_substream_chip(substream);
543 unsigned int channel = (unsigned int)substream->runtime->private_data;
544 unsigned int channel_mask = 1 << channel;
545
546 spin_lock_irq(&chip->reg_lock);
547 oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
548 oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
549
550 chip->interrupt_mask |= channel_mask;
551 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
552 spin_unlock_irq(&chip->reg_lock);
553 return 0;
554}
555
556static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
557{
558 struct oxygen *chip = snd_pcm_substream_chip(substream);
559 struct snd_pcm_substream *s;
560 unsigned int mask = 0;
561 int running;
562
563 switch (cmd) {
564 case SNDRV_PCM_TRIGGER_STOP:
565 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
566 running = 0;
567 break;
568 case SNDRV_PCM_TRIGGER_START:
569 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
570 running = 1;
571 break;
572 default:
573 return -EINVAL;
574 }
575
576 snd_pcm_group_for_each_entry(s, substream) {
577 if (snd_pcm_substream_chip(s) == chip) {
578 mask |= 1 << (unsigned int)s->runtime->private_data;
579 snd_pcm_trigger_done(s, substream);
580 }
581 }
582
583 spin_lock(&chip->reg_lock);
584 if (running)
585 chip->pcm_running |= mask;
586 else
587 chip->pcm_running &= ~mask;
588 oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
589 spin_unlock(&chip->reg_lock);
590 return 0;
591}
592
593static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
594{
595 struct oxygen *chip = snd_pcm_substream_chip(substream);
596 struct snd_pcm_runtime *runtime = substream->runtime;
597 unsigned int channel = (unsigned int)runtime->private_data;
598 u32 curr_addr;
599
600 /* no spinlock, this read should be atomic */
601 curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
602 return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
603}
604
605static struct snd_pcm_ops oxygen_rec_a_ops = {
606 .open = oxygen_rec_a_open,
607 .close = oxygen_close,
608 .ioctl = snd_pcm_lib_ioctl,
609 .hw_params = oxygen_rec_a_hw_params,
610 .hw_free = oxygen_hw_free,
611 .prepare = oxygen_prepare,
612 .trigger = oxygen_trigger,
613 .pointer = oxygen_pointer,
614};
615
616static struct snd_pcm_ops oxygen_rec_b_ops = {
617 .open = oxygen_rec_b_open,
618 .close = oxygen_close,
619 .ioctl = snd_pcm_lib_ioctl,
620 .hw_params = oxygen_rec_b_hw_params,
621 .hw_free = oxygen_hw_free,
622 .prepare = oxygen_prepare,
623 .trigger = oxygen_trigger,
624 .pointer = oxygen_pointer,
625};
626
627static struct snd_pcm_ops oxygen_rec_c_ops = {
628 .open = oxygen_rec_c_open,
629 .close = oxygen_close,
630 .ioctl = snd_pcm_lib_ioctl,
631 .hw_params = oxygen_rec_c_hw_params,
632 .hw_free = oxygen_hw_free,
633 .prepare = oxygen_prepare,
634 .trigger = oxygen_trigger,
635 .pointer = oxygen_pointer,
636};
637
638static struct snd_pcm_ops oxygen_spdif_ops = {
639 .open = oxygen_spdif_open,
640 .close = oxygen_close,
641 .ioctl = snd_pcm_lib_ioctl,
642 .hw_params = oxygen_spdif_hw_params,
643 .hw_free = oxygen_spdif_hw_free,
644 .prepare = oxygen_prepare,
645 .trigger = oxygen_trigger,
646 .pointer = oxygen_pointer,
647};
648
649static struct snd_pcm_ops oxygen_multich_ops = {
650 .open = oxygen_multich_open,
651 .close = oxygen_close,
652 .ioctl = snd_pcm_lib_ioctl,
653 .hw_params = oxygen_multich_hw_params,
654 .hw_free = oxygen_hw_free,
655 .prepare = oxygen_prepare,
656 .trigger = oxygen_trigger,
657 .pointer = oxygen_pointer,
658};
659
660static struct snd_pcm_ops oxygen_ac97_ops = {
661 .open = oxygen_ac97_open,
662 .close = oxygen_close,
663 .ioctl = snd_pcm_lib_ioctl,
664 .hw_params = oxygen_ac97_hw_params,
665 .hw_free = oxygen_hw_free,
666 .prepare = oxygen_prepare,
667 .trigger = oxygen_trigger,
668 .pointer = oxygen_pointer,
669};
670
671static void oxygen_pcm_free(struct snd_pcm *pcm)
672{
673 snd_pcm_lib_preallocate_free_for_all(pcm);
674}
675
676int __devinit oxygen_pcm_init(struct oxygen *chip)
677{
678 struct snd_pcm *pcm;
679 int err;
680
681 err = snd_pcm_new(chip->card, "Analog", 0, 1, 1, &pcm);
682 if (err < 0)
683 return err;
684 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_multich_ops);
685 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
686 chip->model->record_from_dma_b ?
687 &oxygen_rec_b_ops : &oxygen_rec_a_ops);
688 pcm->private_data = chip;
689 pcm->private_free = oxygen_pcm_free;
690 strcpy(pcm->name, "Analog");
691 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
692 SNDRV_DMA_TYPE_DEV,
693 snd_dma_pci_data(chip->pci),
694 512 * 1024, 2048 * 1024);
695 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
696 SNDRV_DMA_TYPE_DEV,
697 snd_dma_pci_data(chip->pci),
698 128 * 1024, 256 * 1024);
699
700 err = snd_pcm_new(chip->card, "Digital", 1, 1, 1, &pcm);
701 if (err < 0)
702 return err;
703 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_spdif_ops);
704 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &oxygen_rec_c_ops);
705 pcm->private_data = chip;
706 pcm->private_free = oxygen_pcm_free;
707 strcpy(pcm->name, "Digital");
708 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
709 snd_dma_pci_data(chip->pci),
710 128 * 1024, 256 * 1024);
711
712 if (chip->has_2nd_ac97_codec) {
713 err = snd_pcm_new(chip->card, "AC97", 2, 1, 0, &pcm);
714 if (err < 0)
715 return err;
716 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
717 &oxygen_ac97_ops);
718 pcm->private_data = chip;
719 pcm->private_free = oxygen_pcm_free;
720 strcpy(pcm->name, "Front Panel");
721 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
722 snd_dma_pci_data(chip->pci),
723 128 * 1024, 256 * 1024);
724 }
725 return 0;
726}
diff --git a/sound/pci/oxygen/oxygen_regs.h b/sound/pci/oxygen/oxygen_regs.h
new file mode 100644
index 000000000000..7a4726d2b2cf
--- /dev/null
+++ b/sound/pci/oxygen/oxygen_regs.h
@@ -0,0 +1,246 @@
1#ifndef OXYGEN_REGS_H_INCLUDED
2#define OXYGEN_REGS_H_INCLUDED
3
4/* recording channel A */
5#define OXYGEN_DMA_A_ADDRESS 0x00 /* 32-bit base address */
6#define OXYGEN_DMA_A_COUNT 0x04 /* buffer counter (dwords) */
7#define OXYGEN_DMA_A_TCOUNT 0x06 /* interrupt counter (dwords) */
8
9/* recording channel B */
10#define OXYGEN_DMA_B_ADDRESS 0x08
11#define OXYGEN_DMA_B_COUNT 0x0c
12#define OXYGEN_DMA_B_TCOUNT 0x0e
13
14/* recording channel C */
15#define OXYGEN_DMA_C_ADDRESS 0x10
16#define OXYGEN_DMA_C_COUNT 0x14
17#define OXYGEN_DMA_C_TCOUNT 0x16
18
19/* SPDIF playback channel */
20#define OXYGEN_DMA_SPDIF_ADDRESS 0x18
21#define OXYGEN_DMA_SPDIF_COUNT 0x1c
22#define OXYGEN_DMA_SPDIF_TCOUNT 0x1e
23
24/* multichannel playback channel */
25#define OXYGEN_DMA_MULTICH_ADDRESS 0x20
26#define OXYGEN_DMA_MULTICH_COUNT 0x24 /* 32 bits */
27#define OXYGEN_DMA_MULTICH_TCOUNT 0x28 /* 32 bits */
28
29/* AC'97 (front panel) playback channel */
30#define OXYGEN_DMA_AC97_ADDRESS 0x30
31#define OXYGEN_DMA_AC97_COUNT 0x34
32#define OXYGEN_DMA_AC97_TCOUNT 0x36
33
34/* all registers 0x00..0x36 return current position on read */
35
36#define OXYGEN_DMA_STATUS 0x40 /* 1 = running, 0 = stop */
37#define OXYGEN_CHANNEL_A 0x01
38#define OXYGEN_CHANNEL_B 0x02
39#define OXYGEN_CHANNEL_C 0x04
40#define OXYGEN_CHANNEL_SPDIF 0x08
41#define OXYGEN_CHANNEL_MULTICH 0x10
42#define OXYGEN_CHANNEL_AC97 0x20
43
44#define OXYGEN_DMA_RESET 0x42
45/* OXYGEN_CHANNEL_* */
46
47#define OXYGEN_PLAY_CHANNELS 0x43
48#define OXYGEN_PLAY_CHANNELS_MASK 0x03
49#define OXYGEN_PLAY_CHANNELS_2 0x00
50#define OXYGEN_PLAY_CHANNELS_4 0x01
51#define OXYGEN_PLAY_CHANNELS_6 0x02
52#define OXYGEN_PLAY_CHANNELS_8 0x03
53
54#define OXYGEN_INTERRUPT_MASK 0x44
55/* OXYGEN_CHANNEL_* */
56#define OXYGEN_INT_SPDIF_IN_CHANGE 0x0100
57#define OXYGEN_INT_GPIO 0x0800
58
59#define OXYGEN_INTERRUPT_STATUS 0x46
60/* OXYGEN_CHANNEL_* amd OXYGEN_INT_* */
61#define OXYGEN_INT_MIDI 0x1000
62
63#define OXYGEN_MISC 0x48
64#define OXYGEN_MISC_MAGIC 0x20
65#define OXYGEN_MISC_MIDI 0x40
66
67#define OXYGEN_REC_FORMAT 0x4a
68#define OXYGEN_REC_FORMAT_A_MASK 0x03
69#define OXYGEN_REC_FORMAT_A_SHIFT 0
70#define OXYGEN_REC_FORMAT_B_MASK 0x0c
71#define OXYGEN_REC_FORMAT_B_SHIFT 2
72#define OXYGEN_REC_FORMAT_C_MASK 0x30
73#define OXYGEN_REC_FORMAT_C_SHIFT 4
74#define OXYGEN_FORMAT_16 0x00
75#define OXYGEN_FORMAT_24 0x01
76#define OXYGEN_FORMAT_32 0x02
77
78#define OXYGEN_PLAY_FORMAT 0x4b
79#define OXYGEN_SPDIF_FORMAT_MASK 0x03
80#define OXYGEN_SPDIF_FORMAT_SHIFT 0
81#define OXYGEN_MULTICH_FORMAT_MASK 0x0c
82#define OXYGEN_MULTICH_FORMAT_SHIFT 2
83#define OXYGEN_AC97_FORMAT_MASK 0x30
84#define OXYGEN_AC97_FORMAT_SHIFT 4
85/* OXYGEN_FORMAT_* */
86
87#define OXYGEN_REC_CHANNELS 0x4c
88#define OXYGEN_REC_A_CHANNELS_MASK 0x07
89#define OXYGEN_REC_CHANNELS_2 0x00
90#define OXYGEN_REC_CHANNELS_4 0x01
91#define OXYGEN_REC_CHANNELS_6 0x03 /* or 0x02 */
92#define OXYGEN_REC_CHANNELS_8 0x04
93
94#define OXYGEN_FUNCTION 0x50
95#define OXYGEN_FUNCTION_RESET_CODEC 0x02
96#define OXYGEN_FUNCTION_ENABLE_SPI_4_5 0x80
97
98#define OXYGEN_I2S_MULTICH_FORMAT 0x60
99#define OXYGEN_I2S_RATE_MASK 0x0007
100#define OXYGEN_RATE_32000 0x0000
101#define OXYGEN_RATE_44100 0x0001
102#define OXYGEN_RATE_48000 0x0002
103#define OXYGEN_RATE_64000 0x0003
104#define OXYGEN_RATE_88200 0x0004
105#define OXYGEN_RATE_96000 0x0005
106#define OXYGEN_RATE_176400 0x0006
107#define OXYGEN_RATE_192000 0x0007
108#define OXYGEN_I2S_MAGIC1_MASK 0x0008
109#define OXYGEN_I2S_MAGIC2_MASK 0x0030
110#define OXYGEN_I2S_FORMAT_MASK 0x00c0
111#define OXYGEN_I2S_FORMAT_16 0x0000
112#define OXYGEN_I2S_FORMAT_20 0x0040
113#define OXYGEN_I2S_FORMAT_24 0x0080
114#define OXYGEN_I2S_FORMAT_32 0x00c0
115
116#define OXYGEN_I2S_A_FORMAT 0x62
117#define OXYGEN_I2S_B_FORMAT 0x64
118#define OXYGEN_I2S_C_FORMAT 0x66
119/* OXYGEN_I2S_RATE_* and OXYGEN_I2S_FORMAT_* */
120
121#define OXYGEN_SPDIF_CONTROL 0x70
122#define OXYGEN_SPDIF_OUT_ENABLE 0x00000002
123#define OXYGEN_SPDIF_LOOPBACK 0x00000004
124#define OXYGEN_SPDIF_MAGIC2 0x00000020
125#define OXYGEN_SPDIF_MAGIC3 0x00000040
126#define OXYGEN_SPDIF_IN_VALID 0x00001000
127#define OXYGEN_SPDIF_IN_CHANGE 0x00008000 /* r/wc */
128#define OXYGEN_SPDIF_IN_INVERT 0x00010000 /* ? */
129#define OXYGEN_SPDIF_OUT_RATE_MASK 0x07000000
130#define OXYGEN_SPDIF_OUT_RATE_SHIFT 24
131/* OXYGEN_RATE_* << OXYGEN_SPDIF_OUT_RATE_SHIFT */
132
133#define OXYGEN_SPDIF_OUTPUT_BITS 0x74
134#define OXYGEN_SPDIF_NONAUDIO 0x00000002
135#define OXYGEN_SPDIF_C 0x00000004
136#define OXYGEN_SPDIF_PREEMPHASIS 0x00000008
137#define OXYGEN_SPDIF_CATEGORY_MASK 0x000007f0
138#define OXYGEN_SPDIF_CATEGORY_SHIFT 4
139#define OXYGEN_SPDIF_ORIGINAL 0x00000800
140#define OXYGEN_SPDIF_CS_RATE_MASK 0x0000f000
141#define OXYGEN_SPDIF_CS_RATE_SHIFT 12
142#define OXYGEN_SPDIF_V 0x00010000 /* 0 = valid */
143
144#define OXYGEN_SPDIF_INPUT_BITS 0x78
145/* 32 bits, IEC958_AES_* */
146
147#define OXYGEN_2WIRE_CONTROL 0x90
148#define OXYGEN_2WIRE_DIR_MASK 0x01
149#define OXYGEN_2WIRE_DIR_WRITE 0x00 /* ? */
150#define OXYGEN_2WIRE_DIR_READ 0x01 /* ? */
151#define OXYGEN_2WIRE_ADDRESS_MASK 0xfe /* slave device address */
152#define OXYGEN_2WIRE_ADDRESS_SHIFT 1
153
154#define OXYGEN_2WIRE_MAP 0x91 /* address, 8 bits */
155#define OXYGEN_2WIRE_DATA 0x92 /* data, 16 bits */
156
157#define OXYGEN_2WIRE_BUS_STATUS 0x94
158#define OXYGEN_2WIRE_BUSY 0x01
159
160#define OXYGEN_SPI_CONTROL 0x98
161#define OXYGEN_SPI_BUSY 0x01 /* read */
162#define OXYGEN_SPI_TRIGGER_WRITE 0x01 /* write */
163#define OXYGEN_SPI_DATA_LENGTH_MASK 0x02
164#define OXYGEN_SPI_DATA_LENGTH_2 0x00
165#define OXYGEN_SPI_DATA_LENGTH_3 0x02
166#define OXYGEN_SPI_CODEC_MASK 0x70 /* 0..5 */
167#define OXYGEN_SPI_CODEC_SHIFT 4
168#define OXYGEN_SPI_MAGIC 0x80
169
170#define OXYGEN_SPI_DATA1 0x99
171#define OXYGEN_SPI_DATA2 0x9a
172#define OXYGEN_SPI_DATA3 0x9b
173
174#define OXYGEN_MPU401 0xa0
175
176#define OXYGEN_GPI_DATA 0xa4
177
178#define OXYGEN_GPI_INTERRUPT_MASK 0xa5
179
180#define OXYGEN_GPIO_DATA 0xa6
181
182#define OXYGEN_GPIO_CONTROL 0xa8
183/* 0: input, 1: output */
184
185#define OXYGEN_GPIO_INTERRUPT_MASK 0xaa
186
187#define OXYGEN_DEVICE_SENSE 0xac /* ? */
188
189#define OXYGEN_PLAY_ROUTING 0xc0
190#define OXYGEN_PLAY_DAC0_SOURCE_MASK 0x0300
191#define OXYGEN_PLAY_DAC1_SOURCE_MASK 0x0700
192#define OXYGEN_PLAY_DAC2_SOURCE_MASK 0x3000
193#define OXYGEN_PLAY_DAC3_SOURCE_MASK 0x7000
194
195#define OXYGEN_REC_ROUTING 0xc2
196
197#define OXYGEN_ADC_MONITOR 0xc3
198#define OXYGEN_ADC_MONITOR_MULTICH 0x01
199#define OXYGEN_ADC_MONITOR_AC97 0x04
200#define OXYGEN_ADC_MONITOR_SPDIF 0x10
201
202#define OXYGEN_A_MONITOR_ROUTING 0xc4
203
204#define OXYGEN_AC97_CONTROL 0xd0
205#define OXYGEN_AC97_RESET1 0x0001
206#define OXYGEN_AC97_RESET1_BUSY 0x0002
207#define OXYGEN_AC97_RESET2 0x0008
208#define OXYGEN_AC97_CODEC_0 0x0010
209#define OXYGEN_AC97_CODEC_1 0x0020
210
211#define OXYGEN_AC97_INTERRUPT_MASK 0xd2
212
213#define OXYGEN_AC97_INTERRUPT_STATUS 0xd3
214#define OXYGEN_AC97_READ_COMPLETE 0x01
215#define OXYGEN_AC97_WRITE_COMPLETE 0x02
216
217#define OXYGEN_AC97_OUT_CONFIG 0xd4
218#define OXYGEN_AC97_OUT_MAGIC1 0x00000011
219#define OXYGEN_AC97_OUT_MAGIC2 0x00000033
220#define OXYGEN_AC97_OUT_MAGIC3 0x0000ff00
221
222#define OXYGEN_AC97_IN_CONFIG 0xd8
223#define OXYGEN_AC97_IN_MAGIC1 0x00000011
224#define OXYGEN_AC97_IN_MAGIC2 0x00000033
225#define OXYGEN_AC97_IN_MAGIC3 0x00000300
226
227#define OXYGEN_AC97_REGS 0xdc
228#define OXYGEN_AC97_REG_DATA_MASK 0x0000ffff
229#define OXYGEN_AC97_REG_ADDR_MASK 0x007f0000
230#define OXYGEN_AC97_REG_ADDR_SHIFT 16
231#define OXYGEN_AC97_REG_DIR_MASK 0x00800000
232#define OXYGEN_AC97_REG_DIR_WRITE 0x00000000
233#define OXYGEN_AC97_REG_DIR_READ 0x00800000
234#define OXYGEN_AC97_REG_CODEC_MASK 0x01000000
235#define OXYGEN_AC97_REG_CODEC_SHIFT 24
236
237#define OXYGEN_DMA_FLUSH 0xe1
238/* OXYGEN_CHANNEL_* */
239
240#define OXYGEN_CODEC_VERSION 0xe4
241
242#define OXYGEN_REVISION 0xe6
243#define OXYGEN_REVISION_2 0x08 /* bit flag */
244#define OXYGEN_REVISION_8787 0x14 /* all 8 bits */
245
246#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 17:00:42 -0500