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authorJyri Sarha <jsarha@ti.com>2014-09-03 08:52:34 -0400
committerMark Brown <broonie@kernel.org>2014-09-03 10:25:44 -0400
commit7ed36e96fd05470e98e7daf648f9cf7f38609670 (patch)
tree952e7724b780e50c6dfdbca3c241694afeb01dcf /sound/soc
parent94fe356f4c6e600379a9949a419e880dfe896e11 (diff)
ASoC: tlv320aic31xx: Choose PLL p divider automatically
This simplifies aic31xx_divs table. There is no more need for p_val or separate lines for 12 and 24 MHz mclks. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc')
-rw-r--r--sound/soc/codecs/tlv320aic31xx.c101
1 files changed, 50 insertions, 51 deletions
diff --git a/sound/soc/codecs/tlv320aic31xx.c b/sound/soc/codecs/tlv320aic31xx.c
index 40a636f447f1..145fe5b253d4 100644
--- a/sound/soc/codecs/tlv320aic31xx.c
+++ b/sound/soc/codecs/tlv320aic31xx.c
@@ -167,13 +167,13 @@ struct aic31xx_priv {
167 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES]; 167 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
168 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES]; 168 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
169 unsigned int sysclk; 169 unsigned int sysclk;
170 u8 p_div;
170 int rate_div_line; 171 int rate_div_line;
171}; 172};
172 173
173struct aic31xx_rate_divs { 174struct aic31xx_rate_divs {
174 u32 mclk; 175 u32 mclk_p;
175 u32 rate; 176 u32 rate;
176 u8 p_val;
177 u8 pll_j; 177 u8 pll_j;
178 u16 pll_d; 178 u16 pll_d;
179 u16 dosr; 179 u16 dosr;
@@ -186,62 +186,51 @@ struct aic31xx_rate_divs {
186 186
187/* ADC dividers can be disabled by cofiguring them to 0 */ 187/* ADC dividers can be disabled by cofiguring them to 0 */
188static const struct aic31xx_rate_divs aic31xx_divs[] = { 188static const struct aic31xx_rate_divs aic31xx_divs[] = {
189 /* mclk rate pll: p j d dosr ndac mdac aors nadc madc */ 189 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */
190 /* 8k rate */ 190 /* 8k rate */
191 {12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2}, 191 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2},
192 {12000000, 8000, 1, 8, 1920, 128, 32, 3, 128, 32, 3}, 192 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3},
193 {24000000, 8000, 2, 8, 1920, 128, 48, 2, 128, 48, 2}, 193 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2},
194 {25000000, 8000, 2, 7, 8643, 128, 48, 2, 128, 48, 2},
195 /* 11.025k rate */ 194 /* 11.025k rate */
196 {12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2}, 195 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2},
197 {12000000, 11025, 1, 8, 4672, 128, 24, 3, 128, 24, 3}, 196 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3},
198 {24000000, 11025, 2, 7, 5264, 128, 32, 2, 128, 32, 2}, 197 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2},
199 {25000000, 11025, 2, 7, 2253, 128, 32, 2, 128, 32, 2},
200 /* 16k rate */ 198 /* 16k rate */
201 {12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2}, 199 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2},
202 {12000000, 16000, 1, 8, 1920, 128, 16, 3, 128, 16, 3}, 200 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3},
203 {24000000, 16000, 2, 8, 1920, 128, 24, 2, 128, 24, 2}, 201 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2},
204 {25000000, 16000, 2, 7, 8643, 128, 24, 2, 128, 24, 2},
205 /* 22.05k rate */ 202 /* 22.05k rate */
206 {12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2}, 203 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2},
207 {12000000, 22050, 1, 8, 4672, 128, 12, 3, 128, 12, 3}, 204 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3},
208 {24000000, 22050, 2, 7, 5264, 128, 16, 2, 128, 16, 2}, 205 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2},
209 {25000000, 22050, 2, 7, 2253, 128, 16, 2, 128, 16, 2},
210 /* 32k rate */ 206 /* 32k rate */
211 {12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2}, 207 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2},
212 {12000000, 32000, 1, 8, 1920, 128, 8, 3, 128, 8, 3}, 208 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3},
213 {24000000, 32000, 2, 8, 1920, 128, 12, 2, 128, 12, 2}, 209 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2},
214 {25000000, 32000, 2, 7, 8643, 128, 12, 2, 128, 12, 2},
215 /* 44.1k rate */ 210 /* 44.1k rate */
216 {12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2}, 211 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2},
217 {12000000, 44100, 1, 8, 4672, 128, 6, 3, 128, 6, 3}, 212 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3},
218 {24000000, 44100, 2, 7, 5264, 128, 8, 2, 128, 8, 2}, 213 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2},
219 {25000000, 44100, 2, 7, 2253, 128, 8, 2, 128, 8, 2},
220 /* 48k rate */ 214 /* 48k rate */
221 {12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2}, 215 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2},
222 {12000000, 48000, 1, 7, 6800, 96, 5, 4, 96, 5, 4}, 216 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4},
223 {24000000, 48000, 2, 8, 1920, 128, 8, 2, 128, 8, 2}, 217 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2},
224 {25000000, 48000, 2, 7, 8643, 128, 8, 2, 128, 8, 2},
225 /* 88.2k rate */ 218 /* 88.2k rate */
226 {12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2}, 219 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2},
227 {12000000, 88200, 1, 8, 4672, 64, 6, 3, 64, 6, 3}, 220 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3},
228 {24000000, 88200, 2, 7, 5264, 64, 8, 2, 64, 8, 2}, 221 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2},
229 {25000000, 88200, 2, 7, 2253, 64, 8, 2, 64, 8, 2},
230 /* 96k rate */ 222 /* 96k rate */
231 {12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2}, 223 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2},
232 {12000000, 96000, 1, 7, 6800, 48, 5, 4, 48, 5, 4}, 224 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4},
233 {24000000, 96000, 2, 8, 1920, 64, 8, 2, 64, 8, 2}, 225 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2},
234 {25000000, 96000, 2, 7, 8643, 64, 8, 2, 64, 8, 2},
235 /* 176.4k rate */ 226 /* 176.4k rate */
236 {12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2}, 227 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2},
237 {12000000, 176400, 1, 8, 4672, 32, 6, 3, 32, 6, 3}, 228 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3},
238 {24000000, 176400, 2, 7, 5264, 32, 8, 2, 32, 8, 2}, 229 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2},
239 {25000000, 176400, 2, 7, 2253, 32, 8, 2, 32, 8, 2},
240 /* 192k rate */ 230 /* 192k rate */
241 {12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2}, 231 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2},
242 {12000000, 192000, 1, 7, 6800, 24, 5, 4, 24, 5, 4}, 232 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4},
243 {24000000, 192000, 2, 8, 1920, 32, 8, 2, 32, 8, 2}, 233 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2},
244 {25000000, 192000, 2, 7, 8643, 32, 8, 2, 32, 8, 2},
245}; 234};
246 235
247static const char * const ldac_in_text[] = { 236static const char * const ldac_in_text[] = {
@@ -692,6 +681,7 @@ static int aic31xx_setup_pll(struct snd_soc_codec *codec,
692{ 681{
693 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 682 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
694 int bclk_score = snd_soc_params_to_frame_size(params); 683 int bclk_score = snd_soc_params_to_frame_size(params);
684 int mclk_p = aic31xx->sysclk / aic31xx->p_div;
695 int bclk_n = 0; 685 int bclk_n = 0;
696 int match = -1; 686 int match = -1;
697 int i; 687 int i;
@@ -704,7 +694,7 @@ static int aic31xx_setup_pll(struct snd_soc_codec *codec,
704 694
705 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) { 695 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
706 if (aic31xx_divs[i].rate == params_rate(params) && 696 if (aic31xx_divs[i].rate == params_rate(params) &&
707 aic31xx_divs[i].mclk == aic31xx->sysclk) { 697 aic31xx_divs[i].mclk_p == mclk_p) {
708 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) % 698 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
709 snd_soc_params_to_frame_size(params); 699 snd_soc_params_to_frame_size(params);
710 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) / 700 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
@@ -738,7 +728,7 @@ static int aic31xx_setup_pll(struct snd_soc_codec *codec,
738 728
739 /* PLL configuration */ 729 /* PLL configuration */
740 snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK, 730 snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
741 (aic31xx_divs[i].p_val << 4) | 0x01); 731 (aic31xx->p_div << 4) | 0x01);
742 snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j); 732 snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
743 733
744 snd_soc_write(codec, AIC31XX_PLLDMSB, 734 snd_soc_write(codec, AIC31XX_PLLDMSB,
@@ -772,7 +762,7 @@ static int aic31xx_setup_pll(struct snd_soc_codec *codec,
772 dev_dbg(codec->dev, 762 dev_dbg(codec->dev,
773 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n", 763 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
774 aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d, 764 aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d,
775 aic31xx_divs[i].p_val, aic31xx_divs[i].dosr, 765 aic31xx->p_div, aic31xx_divs[i].dosr,
776 aic31xx_divs[i].ndac, aic31xx_divs[i].mdac, 766 aic31xx_divs[i].ndac, aic31xx_divs[i].mdac,
777 aic31xx_divs[i].aosr, aic31xx_divs[i].nadc, 767 aic31xx_divs[i].aosr, aic31xx_divs[i].nadc,
778 aic31xx_divs[i].madc, bclk_n); 768 aic31xx_divs[i].madc, bclk_n);
@@ -912,7 +902,16 @@ static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
912 dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n", 902 dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
913 __func__, clk_id, freq, dir); 903 __func__, clk_id, freq, dir);
914 904
915 for (i = 0; aic31xx_divs[i].mclk != freq; i++) { 905 for (i = 1; freq/i > 20000000 && i < 8; i++)
906 ;
907 if (freq/i > 20000000) {
908 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",
909 __func__, freq);
910 return -EINVAL;
911 }
912 aic31xx->p_div = i;
913
914 for (i = 0; aic31xx_divs[i].mclk_p != freq/aic31xx->p_div; i++) {
916 if (i == ARRAY_SIZE(aic31xx_divs)) { 915 if (i == ARRAY_SIZE(aic31xx_divs)) {
917 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n", 916 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
918 __func__, freq); 917 __func__, freq);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-28 16:27:57 -0400