diff options
author | Ola Lilja <ola.o.lilja@stericsson.com> | 2012-05-08 09:57:18 -0400 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2012-05-09 07:52:59 -0400 |
commit | 3592b7f69a5438812381ff0aacdea1725ffa1c1c (patch) | |
tree | b24451a32b623d2d1ce71031bdc9033195129fec /sound/soc/ux500/ux500_msp_i2s.c | |
parent | 41a41eaca48946a69bb0a1f6e053b9e4f1458e15 (diff) |
ASoC: Ux500: Add MSP I2S-driver
Add driver for running I2S with the MSP-block.
Signed-off-by: Ola Lilja <ola.o.lilja@stericsson.com>
[Fixed trailing whitespace -- broonie]
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/ux500/ux500_msp_i2s.c')
-rw-r--r-- | sound/soc/ux500/ux500_msp_i2s.c | 742 |
1 files changed, 742 insertions, 0 deletions
diff --git a/sound/soc/ux500/ux500_msp_i2s.c b/sound/soc/ux500/ux500_msp_i2s.c new file mode 100644 index 000000000000..496dec10c96e --- /dev/null +++ b/sound/soc/ux500/ux500_msp_i2s.c | |||
@@ -0,0 +1,742 @@ | |||
1 | /* | ||
2 | * Copyright (C) ST-Ericsson SA 2012 | ||
3 | * | ||
4 | * Author: Ola Lilja <ola.o.lilja@stericsson.com>, | ||
5 | * Roger Nilsson <roger.xr.nilsson@stericsson.com>, | ||
6 | * Sandeep Kaushik <sandeep.kaushik@st.com> | ||
7 | * for ST-Ericsson. | ||
8 | * | ||
9 | * License terms: | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as published | ||
13 | * by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/module.h> | ||
17 | #include <linux/platform_device.h> | ||
18 | #include <linux/delay.h> | ||
19 | #include <linux/slab.h> | ||
20 | |||
21 | #include <mach/hardware.h> | ||
22 | #include <mach/board-mop500-msp.h> | ||
23 | |||
24 | #include <sound/soc.h> | ||
25 | |||
26 | #include "ux500_msp_i2s.h" | ||
27 | |||
28 | /* Protocol desciptors */ | ||
29 | static const struct msp_protdesc prot_descs[] = { | ||
30 | { /* I2S */ | ||
31 | MSP_SINGLE_PHASE, | ||
32 | MSP_SINGLE_PHASE, | ||
33 | MSP_PHASE2_START_MODE_IMEDIATE, | ||
34 | MSP_PHASE2_START_MODE_IMEDIATE, | ||
35 | MSP_BTF_MS_BIT_FIRST, | ||
36 | MSP_BTF_MS_BIT_FIRST, | ||
37 | MSP_FRAME_LEN_1, | ||
38 | MSP_FRAME_LEN_1, | ||
39 | MSP_FRAME_LEN_1, | ||
40 | MSP_FRAME_LEN_1, | ||
41 | MSP_ELEM_LEN_32, | ||
42 | MSP_ELEM_LEN_32, | ||
43 | MSP_ELEM_LEN_32, | ||
44 | MSP_ELEM_LEN_32, | ||
45 | MSP_DELAY_1, | ||
46 | MSP_DELAY_1, | ||
47 | MSP_RISING_EDGE, | ||
48 | MSP_FALLING_EDGE, | ||
49 | MSP_FSYNC_POL_ACT_LO, | ||
50 | MSP_FSYNC_POL_ACT_LO, | ||
51 | MSP_SWAP_NONE, | ||
52 | MSP_SWAP_NONE, | ||
53 | MSP_COMPRESS_MODE_LINEAR, | ||
54 | MSP_EXPAND_MODE_LINEAR, | ||
55 | MSP_FSYNC_IGNORE, | ||
56 | 31, | ||
57 | 15, | ||
58 | 32, | ||
59 | }, { /* PCM */ | ||
60 | MSP_DUAL_PHASE, | ||
61 | MSP_DUAL_PHASE, | ||
62 | MSP_PHASE2_START_MODE_FSYNC, | ||
63 | MSP_PHASE2_START_MODE_FSYNC, | ||
64 | MSP_BTF_MS_BIT_FIRST, | ||
65 | MSP_BTF_MS_BIT_FIRST, | ||
66 | MSP_FRAME_LEN_1, | ||
67 | MSP_FRAME_LEN_1, | ||
68 | MSP_FRAME_LEN_1, | ||
69 | MSP_FRAME_LEN_1, | ||
70 | MSP_ELEM_LEN_16, | ||
71 | MSP_ELEM_LEN_16, | ||
72 | MSP_ELEM_LEN_16, | ||
73 | MSP_ELEM_LEN_16, | ||
74 | MSP_DELAY_0, | ||
75 | MSP_DELAY_0, | ||
76 | MSP_RISING_EDGE, | ||
77 | MSP_FALLING_EDGE, | ||
78 | MSP_FSYNC_POL_ACT_HI, | ||
79 | MSP_FSYNC_POL_ACT_HI, | ||
80 | MSP_SWAP_NONE, | ||
81 | MSP_SWAP_NONE, | ||
82 | MSP_COMPRESS_MODE_LINEAR, | ||
83 | MSP_EXPAND_MODE_LINEAR, | ||
84 | MSP_FSYNC_IGNORE, | ||
85 | 255, | ||
86 | 0, | ||
87 | 256, | ||
88 | }, { /* Companded PCM */ | ||
89 | MSP_SINGLE_PHASE, | ||
90 | MSP_SINGLE_PHASE, | ||
91 | MSP_PHASE2_START_MODE_FSYNC, | ||
92 | MSP_PHASE2_START_MODE_FSYNC, | ||
93 | MSP_BTF_MS_BIT_FIRST, | ||
94 | MSP_BTF_MS_BIT_FIRST, | ||
95 | MSP_FRAME_LEN_1, | ||
96 | MSP_FRAME_LEN_1, | ||
97 | MSP_FRAME_LEN_1, | ||
98 | MSP_FRAME_LEN_1, | ||
99 | MSP_ELEM_LEN_8, | ||
100 | MSP_ELEM_LEN_8, | ||
101 | MSP_ELEM_LEN_8, | ||
102 | MSP_ELEM_LEN_8, | ||
103 | MSP_DELAY_0, | ||
104 | MSP_DELAY_0, | ||
105 | MSP_RISING_EDGE, | ||
106 | MSP_RISING_EDGE, | ||
107 | MSP_FSYNC_POL_ACT_HI, | ||
108 | MSP_FSYNC_POL_ACT_HI, | ||
109 | MSP_SWAP_NONE, | ||
110 | MSP_SWAP_NONE, | ||
111 | MSP_COMPRESS_MODE_LINEAR, | ||
112 | MSP_EXPAND_MODE_LINEAR, | ||
113 | MSP_FSYNC_IGNORE, | ||
114 | 255, | ||
115 | 0, | ||
116 | 256, | ||
117 | }, | ||
118 | }; | ||
119 | |||
120 | static void set_prot_desc_tx(struct ux500_msp *msp, | ||
121 | struct msp_protdesc *protdesc, | ||
122 | enum msp_data_size data_size) | ||
123 | { | ||
124 | u32 temp_reg = 0; | ||
125 | |||
126 | temp_reg |= MSP_P2_ENABLE_BIT(protdesc->tx_phase_mode); | ||
127 | temp_reg |= MSP_P2_START_MODE_BIT(protdesc->tx_phase2_start_mode); | ||
128 | temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->tx_frame_len_1); | ||
129 | temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->tx_frame_len_2); | ||
130 | if (msp->def_elem_len) { | ||
131 | temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->tx_elem_len_1); | ||
132 | temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->tx_elem_len_2); | ||
133 | } else { | ||
134 | temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size); | ||
135 | temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size); | ||
136 | } | ||
137 | temp_reg |= MSP_DATA_DELAY_BITS(protdesc->tx_data_delay); | ||
138 | temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->tx_byte_order); | ||
139 | temp_reg |= MSP_FSYNC_POL(protdesc->tx_fsync_pol); | ||
140 | temp_reg |= MSP_DATA_WORD_SWAP(protdesc->tx_half_word_swap); | ||
141 | temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->compression_mode); | ||
142 | temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore); | ||
143 | |||
144 | writel(temp_reg, msp->registers + MSP_TCF); | ||
145 | } | ||
146 | |||
147 | static void set_prot_desc_rx(struct ux500_msp *msp, | ||
148 | struct msp_protdesc *protdesc, | ||
149 | enum msp_data_size data_size) | ||
150 | { | ||
151 | u32 temp_reg = 0; | ||
152 | |||
153 | temp_reg |= MSP_P2_ENABLE_BIT(protdesc->rx_phase_mode); | ||
154 | temp_reg |= MSP_P2_START_MODE_BIT(protdesc->rx_phase2_start_mode); | ||
155 | temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->rx_frame_len_1); | ||
156 | temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->rx_frame_len_2); | ||
157 | if (msp->def_elem_len) { | ||
158 | temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->rx_elem_len_1); | ||
159 | temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->rx_elem_len_2); | ||
160 | } else { | ||
161 | temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size); | ||
162 | temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size); | ||
163 | } | ||
164 | |||
165 | temp_reg |= MSP_DATA_DELAY_BITS(protdesc->rx_data_delay); | ||
166 | temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->rx_byte_order); | ||
167 | temp_reg |= MSP_FSYNC_POL(protdesc->rx_fsync_pol); | ||
168 | temp_reg |= MSP_DATA_WORD_SWAP(protdesc->rx_half_word_swap); | ||
169 | temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->expansion_mode); | ||
170 | temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore); | ||
171 | |||
172 | writel(temp_reg, msp->registers + MSP_RCF); | ||
173 | } | ||
174 | |||
175 | static int configure_protocol(struct ux500_msp *msp, | ||
176 | struct ux500_msp_config *config) | ||
177 | { | ||
178 | struct msp_protdesc *protdesc; | ||
179 | enum msp_data_size data_size; | ||
180 | u32 temp_reg = 0; | ||
181 | |||
182 | data_size = config->data_size; | ||
183 | msp->def_elem_len = config->def_elem_len; | ||
184 | if (config->default_protdesc == 1) { | ||
185 | if (config->protocol >= MSP_INVALID_PROTOCOL) { | ||
186 | dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n", | ||
187 | __func__); | ||
188 | return -EINVAL; | ||
189 | } | ||
190 | protdesc = | ||
191 | (struct msp_protdesc *)&prot_descs[config->protocol]; | ||
192 | } else { | ||
193 | protdesc = (struct msp_protdesc *)&config->protdesc; | ||
194 | } | ||
195 | |||
196 | if (data_size < MSP_DATA_BITS_DEFAULT || data_size > MSP_DATA_BITS_32) { | ||
197 | dev_err(msp->dev, | ||
198 | "%s: ERROR: Invalid data-size requested (data_size = %d)!\n", | ||
199 | __func__, data_size); | ||
200 | return -EINVAL; | ||
201 | } | ||
202 | |||
203 | if (config->direction & MSP_DIR_TX) | ||
204 | set_prot_desc_tx(msp, protdesc, data_size); | ||
205 | if (config->direction & MSP_DIR_RX) | ||
206 | set_prot_desc_rx(msp, protdesc, data_size); | ||
207 | |||
208 | /* The code below should not be separated. */ | ||
209 | temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; | ||
210 | temp_reg |= MSP_TX_CLKPOL_BIT(~protdesc->tx_clk_pol); | ||
211 | writel(temp_reg, msp->registers + MSP_GCR); | ||
212 | temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; | ||
213 | temp_reg |= MSP_RX_CLKPOL_BIT(protdesc->rx_clk_pol); | ||
214 | writel(temp_reg, msp->registers + MSP_GCR); | ||
215 | |||
216 | return 0; | ||
217 | } | ||
218 | |||
219 | static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config) | ||
220 | { | ||
221 | u32 reg_val_GCR; | ||
222 | u32 frame_per = 0; | ||
223 | u32 sck_div = 0; | ||
224 | u32 frame_width = 0; | ||
225 | u32 temp_reg = 0; | ||
226 | struct msp_protdesc *protdesc = NULL; | ||
227 | |||
228 | reg_val_GCR = readl(msp->registers + MSP_GCR); | ||
229 | writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); | ||
230 | |||
231 | if (config->default_protdesc) | ||
232 | protdesc = | ||
233 | (struct msp_protdesc *)&prot_descs[config->protocol]; | ||
234 | else | ||
235 | protdesc = (struct msp_protdesc *)&config->protdesc; | ||
236 | |||
237 | switch (config->protocol) { | ||
238 | case MSP_PCM_PROTOCOL: | ||
239 | case MSP_PCM_COMPAND_PROTOCOL: | ||
240 | frame_width = protdesc->frame_width; | ||
241 | sck_div = config->f_inputclk / (config->frame_freq * | ||
242 | (protdesc->clocks_per_frame)); | ||
243 | frame_per = protdesc->frame_period; | ||
244 | break; | ||
245 | case MSP_I2S_PROTOCOL: | ||
246 | frame_width = protdesc->frame_width; | ||
247 | sck_div = config->f_inputclk / (config->frame_freq * | ||
248 | (protdesc->clocks_per_frame)); | ||
249 | frame_per = protdesc->frame_period; | ||
250 | break; | ||
251 | default: | ||
252 | dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n", | ||
253 | __func__, | ||
254 | config->protocol); | ||
255 | return -EINVAL; | ||
256 | } | ||
257 | |||
258 | temp_reg = (sck_div - 1) & SCK_DIV_MASK; | ||
259 | temp_reg |= FRAME_WIDTH_BITS(frame_width); | ||
260 | temp_reg |= FRAME_PERIOD_BITS(frame_per); | ||
261 | writel(temp_reg, msp->registers + MSP_SRG); | ||
262 | |||
263 | msp->f_bitclk = (config->f_inputclk)/(sck_div + 1); | ||
264 | |||
265 | /* Enable bit-clock */ | ||
266 | udelay(100); | ||
267 | reg_val_GCR = readl(msp->registers + MSP_GCR); | ||
268 | writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); | ||
269 | udelay(100); | ||
270 | |||
271 | return 0; | ||
272 | } | ||
273 | |||
274 | static int configure_multichannel(struct ux500_msp *msp, | ||
275 | struct ux500_msp_config *config) | ||
276 | { | ||
277 | struct msp_protdesc *protdesc; | ||
278 | struct msp_multichannel_config *mcfg; | ||
279 | u32 reg_val_MCR; | ||
280 | |||
281 | if (config->default_protdesc == 1) { | ||
282 | if (config->protocol >= MSP_INVALID_PROTOCOL) { | ||
283 | dev_err(msp->dev, | ||
284 | "%s: ERROR: Invalid protocol (%d)!\n", | ||
285 | __func__, config->protocol); | ||
286 | return -EINVAL; | ||
287 | } | ||
288 | protdesc = (struct msp_protdesc *) | ||
289 | &prot_descs[config->protocol]; | ||
290 | } else { | ||
291 | protdesc = (struct msp_protdesc *)&config->protdesc; | ||
292 | } | ||
293 | |||
294 | mcfg = &config->multichannel_config; | ||
295 | if (mcfg->tx_multichannel_enable) { | ||
296 | if (protdesc->tx_phase_mode == MSP_SINGLE_PHASE) { | ||
297 | reg_val_MCR = readl(msp->registers + MSP_MCR); | ||
298 | writel(reg_val_MCR | (mcfg->tx_multichannel_enable ? | ||
299 | 1 << TMCEN_BIT : 0), | ||
300 | msp->registers + MSP_MCR); | ||
301 | writel(mcfg->tx_channel_0_enable, | ||
302 | msp->registers + MSP_TCE0); | ||
303 | writel(mcfg->tx_channel_1_enable, | ||
304 | msp->registers + MSP_TCE1); | ||
305 | writel(mcfg->tx_channel_2_enable, | ||
306 | msp->registers + MSP_TCE2); | ||
307 | writel(mcfg->tx_channel_3_enable, | ||
308 | msp->registers + MSP_TCE3); | ||
309 | } else { | ||
310 | dev_err(msp->dev, | ||
311 | "%s: ERROR: Only single-phase supported (TX-mode: %d)!\n", | ||
312 | __func__, protdesc->tx_phase_mode); | ||
313 | return -EINVAL; | ||
314 | } | ||
315 | } | ||
316 | if (mcfg->rx_multichannel_enable) { | ||
317 | if (protdesc->rx_phase_mode == MSP_SINGLE_PHASE) { | ||
318 | reg_val_MCR = readl(msp->registers + MSP_MCR); | ||
319 | writel(reg_val_MCR | (mcfg->rx_multichannel_enable ? | ||
320 | 1 << RMCEN_BIT : 0), | ||
321 | msp->registers + MSP_MCR); | ||
322 | writel(mcfg->rx_channel_0_enable, | ||
323 | msp->registers + MSP_RCE0); | ||
324 | writel(mcfg->rx_channel_1_enable, | ||
325 | msp->registers + MSP_RCE1); | ||
326 | writel(mcfg->rx_channel_2_enable, | ||
327 | msp->registers + MSP_RCE2); | ||
328 | writel(mcfg->rx_channel_3_enable, | ||
329 | msp->registers + MSP_RCE3); | ||
330 | } else { | ||
331 | dev_err(msp->dev, | ||
332 | "%s: ERROR: Only single-phase supported (RX-mode: %d)!\n", | ||
333 | __func__, protdesc->rx_phase_mode); | ||
334 | return -EINVAL; | ||
335 | } | ||
336 | if (mcfg->rx_comparison_enable_mode) { | ||
337 | reg_val_MCR = readl(msp->registers + MSP_MCR); | ||
338 | writel(reg_val_MCR | | ||
339 | (mcfg->rx_comparison_enable_mode << RCMPM_BIT), | ||
340 | msp->registers + MSP_MCR); | ||
341 | |||
342 | writel(mcfg->comparison_mask, | ||
343 | msp->registers + MSP_RCM); | ||
344 | writel(mcfg->comparison_value, | ||
345 | msp->registers + MSP_RCV); | ||
346 | |||
347 | } | ||
348 | } | ||
349 | |||
350 | return 0; | ||
351 | } | ||
352 | |||
353 | static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config) | ||
354 | { | ||
355 | int status = 0; | ||
356 | u32 reg_val_DMACR, reg_val_GCR; | ||
357 | |||
358 | /* Check msp state whether in RUN or CONFIGURED Mode */ | ||
359 | if ((msp->msp_state == MSP_STATE_IDLE) && (msp->plat_init)) { | ||
360 | status = msp->plat_init(); | ||
361 | if (status) { | ||
362 | dev_err(msp->dev, "%s: ERROR: Failed to init MSP (%d)!\n", | ||
363 | __func__, status); | ||
364 | return status; | ||
365 | } | ||
366 | } | ||
367 | |||
368 | /* Configure msp with protocol dependent settings */ | ||
369 | configure_protocol(msp, config); | ||
370 | setup_bitclk(msp, config); | ||
371 | if (config->multichannel_configured == 1) { | ||
372 | status = configure_multichannel(msp, config); | ||
373 | if (status) | ||
374 | dev_warn(msp->dev, | ||
375 | "%s: WARN: configure_multichannel failed (%d)!\n", | ||
376 | __func__, status); | ||
377 | } | ||
378 | |||
379 | /* Make sure the correct DMA-directions are configured */ | ||
380 | if ((config->direction & MSP_DIR_RX) && (!msp->dma_cfg_rx)) { | ||
381 | dev_err(msp->dev, "%s: ERROR: MSP RX-mode is not configured!", | ||
382 | __func__); | ||
383 | return -EINVAL; | ||
384 | } | ||
385 | if ((config->direction == MSP_DIR_TX) && (!msp->dma_cfg_tx)) { | ||
386 | dev_err(msp->dev, "%s: ERROR: MSP TX-mode is not configured!", | ||
387 | __func__); | ||
388 | return -EINVAL; | ||
389 | } | ||
390 | |||
391 | reg_val_DMACR = readl(msp->registers + MSP_DMACR); | ||
392 | if (config->direction & MSP_DIR_RX) | ||
393 | reg_val_DMACR |= RX_DMA_ENABLE; | ||
394 | if (config->direction & MSP_DIR_TX) | ||
395 | reg_val_DMACR |= TX_DMA_ENABLE; | ||
396 | writel(reg_val_DMACR, msp->registers + MSP_DMACR); | ||
397 | |||
398 | writel(config->iodelay, msp->registers + MSP_IODLY); | ||
399 | |||
400 | /* Enable frame generation logic */ | ||
401 | reg_val_GCR = readl(msp->registers + MSP_GCR); | ||
402 | writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR); | ||
403 | |||
404 | return status; | ||
405 | } | ||
406 | |||
407 | static void flush_fifo_rx(struct ux500_msp *msp) | ||
408 | { | ||
409 | u32 reg_val_DR, reg_val_GCR, reg_val_FLR; | ||
410 | u32 limit = 32; | ||
411 | |||
412 | reg_val_GCR = readl(msp->registers + MSP_GCR); | ||
413 | writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR); | ||
414 | |||
415 | reg_val_FLR = readl(msp->registers + MSP_FLR); | ||
416 | while (!(reg_val_FLR & RX_FIFO_EMPTY) && limit--) { | ||
417 | reg_val_DR = readl(msp->registers + MSP_DR); | ||
418 | reg_val_FLR = readl(msp->registers + MSP_FLR); | ||
419 | } | ||
420 | |||
421 | writel(reg_val_GCR, msp->registers + MSP_GCR); | ||
422 | } | ||
423 | |||
424 | static void flush_fifo_tx(struct ux500_msp *msp) | ||
425 | { | ||
426 | u32 reg_val_TSTDR, reg_val_GCR, reg_val_FLR; | ||
427 | u32 limit = 32; | ||
428 | |||
429 | reg_val_GCR = readl(msp->registers + MSP_GCR); | ||
430 | writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR); | ||
431 | writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR); | ||
432 | |||
433 | reg_val_FLR = readl(msp->registers + MSP_FLR); | ||
434 | while (!(reg_val_FLR & TX_FIFO_EMPTY) && limit--) { | ||
435 | reg_val_TSTDR = readl(msp->registers + MSP_TSTDR); | ||
436 | reg_val_FLR = readl(msp->registers + MSP_FLR); | ||
437 | } | ||
438 | writel(0x0, msp->registers + MSP_ITCR); | ||
439 | writel(reg_val_GCR, msp->registers + MSP_GCR); | ||
440 | } | ||
441 | |||
442 | int ux500_msp_i2s_open(struct ux500_msp *msp, | ||
443 | struct ux500_msp_config *config) | ||
444 | { | ||
445 | u32 old_reg, new_reg, mask; | ||
446 | int res; | ||
447 | unsigned int tx_sel, rx_sel, tx_busy, rx_busy; | ||
448 | |||
449 | if (in_interrupt()) { | ||
450 | dev_err(msp->dev, | ||
451 | "%s: ERROR: Open called in interrupt context!\n", | ||
452 | __func__); | ||
453 | return -1; | ||
454 | } | ||
455 | |||
456 | tx_sel = (config->direction & MSP_DIR_TX) > 0; | ||
457 | rx_sel = (config->direction & MSP_DIR_RX) > 0; | ||
458 | if (!tx_sel && !rx_sel) { | ||
459 | dev_err(msp->dev, "%s: Error: No direction selected!\n", | ||
460 | __func__); | ||
461 | return -EINVAL; | ||
462 | } | ||
463 | |||
464 | tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0; | ||
465 | rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0; | ||
466 | if (tx_busy && tx_sel) { | ||
467 | dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__); | ||
468 | return -EBUSY; | ||
469 | } | ||
470 | if (rx_busy && rx_sel) { | ||
471 | dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__); | ||
472 | return -EBUSY; | ||
473 | } | ||
474 | |||
475 | msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0); | ||
476 | |||
477 | /* First do the global config register */ | ||
478 | mask = RX_CLK_SEL_MASK | TX_CLK_SEL_MASK | RX_FSYNC_MASK | | ||
479 | TX_FSYNC_MASK | RX_SYNC_SEL_MASK | TX_SYNC_SEL_MASK | | ||
480 | RX_FIFO_ENABLE_MASK | TX_FIFO_ENABLE_MASK | SRG_CLK_SEL_MASK | | ||
481 | LOOPBACK_MASK | TX_EXTRA_DELAY_MASK; | ||
482 | |||
483 | new_reg = (config->tx_clk_sel | config->rx_clk_sel | | ||
484 | config->rx_fsync_pol | config->tx_fsync_pol | | ||
485 | config->rx_fsync_sel | config->tx_fsync_sel | | ||
486 | config->rx_fifo_config | config->tx_fifo_config | | ||
487 | config->srg_clk_sel | config->loopback_enable | | ||
488 | config->tx_data_enable); | ||
489 | |||
490 | old_reg = readl(msp->registers + MSP_GCR); | ||
491 | old_reg &= ~mask; | ||
492 | new_reg |= old_reg; | ||
493 | writel(new_reg, msp->registers + MSP_GCR); | ||
494 | |||
495 | res = enable_msp(msp, config); | ||
496 | if (res < 0) { | ||
497 | dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n", | ||
498 | __func__, res); | ||
499 | return -EBUSY; | ||
500 | } | ||
501 | if (config->loopback_enable & 0x80) | ||
502 | msp->loopback_enable = 1; | ||
503 | |||
504 | /* Flush FIFOs */ | ||
505 | flush_fifo_tx(msp); | ||
506 | flush_fifo_rx(msp); | ||
507 | |||
508 | msp->msp_state = MSP_STATE_CONFIGURED; | ||
509 | return 0; | ||
510 | } | ||
511 | |||
512 | static void disable_msp_rx(struct ux500_msp *msp) | ||
513 | { | ||
514 | u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC; | ||
515 | |||
516 | reg_val_GCR = readl(msp->registers + MSP_GCR); | ||
517 | writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR); | ||
518 | reg_val_DMACR = readl(msp->registers + MSP_DMACR); | ||
519 | writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR); | ||
520 | reg_val_IMSC = readl(msp->registers + MSP_IMSC); | ||
521 | writel(reg_val_IMSC & | ||
522 | ~(RX_SERVICE_INT | RX_OVERRUN_ERROR_INT), | ||
523 | msp->registers + MSP_IMSC); | ||
524 | |||
525 | msp->dir_busy &= ~MSP_DIR_RX; | ||
526 | } | ||
527 | |||
528 | static void disable_msp_tx(struct ux500_msp *msp) | ||
529 | { | ||
530 | u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC; | ||
531 | |||
532 | reg_val_GCR = readl(msp->registers + MSP_GCR); | ||
533 | writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR); | ||
534 | reg_val_DMACR = readl(msp->registers + MSP_DMACR); | ||
535 | writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR); | ||
536 | reg_val_IMSC = readl(msp->registers + MSP_IMSC); | ||
537 | writel(reg_val_IMSC & | ||
538 | ~(TX_SERVICE_INT | TX_UNDERRUN_ERR_INT), | ||
539 | msp->registers + MSP_IMSC); | ||
540 | |||
541 | msp->dir_busy &= ~MSP_DIR_TX; | ||
542 | } | ||
543 | |||
544 | static int disable_msp(struct ux500_msp *msp, unsigned int dir) | ||
545 | { | ||
546 | u32 reg_val_GCR; | ||
547 | int status = 0; | ||
548 | unsigned int disable_tx, disable_rx; | ||
549 | |||
550 | reg_val_GCR = readl(msp->registers + MSP_GCR); | ||
551 | disable_tx = dir & MSP_DIR_TX; | ||
552 | disable_rx = dir & MSP_DIR_TX; | ||
553 | if (disable_tx && disable_rx) { | ||
554 | reg_val_GCR = readl(msp->registers + MSP_GCR); | ||
555 | writel(reg_val_GCR | LOOPBACK_MASK, | ||
556 | msp->registers + MSP_GCR); | ||
557 | |||
558 | /* Flush TX-FIFO */ | ||
559 | flush_fifo_tx(msp); | ||
560 | |||
561 | /* Disable TX-channel */ | ||
562 | writel((readl(msp->registers + MSP_GCR) & | ||
563 | (~TX_ENABLE)), msp->registers + MSP_GCR); | ||
564 | |||
565 | /* Flush RX-FIFO */ | ||
566 | flush_fifo_rx(msp); | ||
567 | |||
568 | /* Disable Loopback and Receive channel */ | ||
569 | writel((readl(msp->registers + MSP_GCR) & | ||
570 | (~(RX_ENABLE | LOOPBACK_MASK))), | ||
571 | msp->registers + MSP_GCR); | ||
572 | |||
573 | disable_msp_tx(msp); | ||
574 | disable_msp_rx(msp); | ||
575 | } else if (disable_tx) | ||
576 | disable_msp_tx(msp); | ||
577 | else if (disable_rx) | ||
578 | disable_msp_rx(msp); | ||
579 | |||
580 | return status; | ||
581 | } | ||
582 | |||
583 | int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction) | ||
584 | { | ||
585 | u32 reg_val_GCR, enable_bit; | ||
586 | |||
587 | if (msp->msp_state == MSP_STATE_IDLE) { | ||
588 | dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n", | ||
589 | __func__); | ||
590 | return -EINVAL; | ||
591 | } | ||
592 | |||
593 | switch (cmd) { | ||
594 | case SNDRV_PCM_TRIGGER_START: | ||
595 | case SNDRV_PCM_TRIGGER_RESUME: | ||
596 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | ||
597 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | ||
598 | enable_bit = TX_ENABLE; | ||
599 | else | ||
600 | enable_bit = RX_ENABLE; | ||
601 | reg_val_GCR = readl(msp->registers + MSP_GCR); | ||
602 | writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR); | ||
603 | break; | ||
604 | |||
605 | case SNDRV_PCM_TRIGGER_STOP: | ||
606 | case SNDRV_PCM_TRIGGER_SUSPEND: | ||
607 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | ||
608 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | ||
609 | disable_msp_tx(msp); | ||
610 | else | ||
611 | disable_msp_rx(msp); | ||
612 | break; | ||
613 | default: | ||
614 | return -EINVAL; | ||
615 | break; | ||
616 | } | ||
617 | |||
618 | return 0; | ||
619 | } | ||
620 | |||
621 | int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir) | ||
622 | { | ||
623 | int status = 0; | ||
624 | |||
625 | dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir); | ||
626 | |||
627 | status = disable_msp(msp, dir); | ||
628 | if (msp->dir_busy == 0) { | ||
629 | /* disable sample rate and frame generators */ | ||
630 | msp->msp_state = MSP_STATE_IDLE; | ||
631 | writel((readl(msp->registers + MSP_GCR) & | ||
632 | (~(FRAME_GEN_ENABLE | SRG_ENABLE))), | ||
633 | msp->registers + MSP_GCR); | ||
634 | if (msp->plat_exit) | ||
635 | status = msp->plat_exit(); | ||
636 | if (status) | ||
637 | dev_warn(msp->dev, | ||
638 | "%s: WARN: ux500_msp_i2s_exit failed (%d)!\n", | ||
639 | __func__, status); | ||
640 | writel(0, msp->registers + MSP_GCR); | ||
641 | writel(0, msp->registers + MSP_TCF); | ||
642 | writel(0, msp->registers + MSP_RCF); | ||
643 | writel(0, msp->registers + MSP_DMACR); | ||
644 | writel(0, msp->registers + MSP_SRG); | ||
645 | writel(0, msp->registers + MSP_MCR); | ||
646 | writel(0, msp->registers + MSP_RCM); | ||
647 | writel(0, msp->registers + MSP_RCV); | ||
648 | writel(0, msp->registers + MSP_TCE0); | ||
649 | writel(0, msp->registers + MSP_TCE1); | ||
650 | writel(0, msp->registers + MSP_TCE2); | ||
651 | writel(0, msp->registers + MSP_TCE3); | ||
652 | writel(0, msp->registers + MSP_RCE0); | ||
653 | writel(0, msp->registers + MSP_RCE1); | ||
654 | writel(0, msp->registers + MSP_RCE2); | ||
655 | writel(0, msp->registers + MSP_RCE3); | ||
656 | } | ||
657 | |||
658 | return status; | ||
659 | |||
660 | } | ||
661 | |||
662 | int ux500_msp_i2s_init_msp(struct platform_device *pdev, | ||
663 | struct ux500_msp **msp_p, | ||
664 | struct msp_i2s_platform_data *platform_data) | ||
665 | { | ||
666 | int ret = 0; | ||
667 | struct resource *res = NULL; | ||
668 | struct i2s_controller *i2s_cont; | ||
669 | struct ux500_msp *msp; | ||
670 | |||
671 | dev_dbg(&pdev->dev, "%s: Enter (name: %s, id: %d).\n", __func__, | ||
672 | pdev->name, platform_data->id); | ||
673 | |||
674 | *msp_p = devm_kzalloc(&pdev->dev, sizeof(struct ux500_msp), GFP_KERNEL); | ||
675 | msp = *msp_p; | ||
676 | |||
677 | msp->id = platform_data->id; | ||
678 | msp->dev = &pdev->dev; | ||
679 | msp->plat_init = platform_data->msp_i2s_init; | ||
680 | msp->plat_exit = platform_data->msp_i2s_exit; | ||
681 | msp->dma_cfg_rx = platform_data->msp_i2s_dma_rx; | ||
682 | msp->dma_cfg_tx = platform_data->msp_i2s_dma_tx; | ||
683 | |||
684 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
685 | if (res == NULL) { | ||
686 | dev_err(&pdev->dev, "%s: ERROR: Unable to get resource!\n", | ||
687 | __func__); | ||
688 | ret = -ENOMEM; | ||
689 | goto err_res; | ||
690 | } | ||
691 | |||
692 | msp->registers = ioremap(res->start, (res->end - res->start + 1)); | ||
693 | if (msp->registers == NULL) { | ||
694 | dev_err(&pdev->dev, "%s: ERROR: ioremap failed!\n", __func__); | ||
695 | ret = -ENOMEM; | ||
696 | goto err_res; | ||
697 | } | ||
698 | |||
699 | msp->msp_state = MSP_STATE_IDLE; | ||
700 | msp->loopback_enable = 0; | ||
701 | |||
702 | /* I2S-controller is allocated and added in I2S controller class. */ | ||
703 | i2s_cont = devm_kzalloc(&pdev->dev, sizeof(*i2s_cont), GFP_KERNEL); | ||
704 | if (!i2s_cont) { | ||
705 | dev_err(&pdev->dev, | ||
706 | "%s: ERROR: Failed to allocate I2S-controller!\n", | ||
707 | __func__); | ||
708 | goto err_i2s_cont; | ||
709 | } | ||
710 | i2s_cont->dev.parent = &pdev->dev; | ||
711 | i2s_cont->data = (void *)msp; | ||
712 | i2s_cont->id = (s16)msp->id; | ||
713 | snprintf(i2s_cont->name, sizeof(i2s_cont->name), "ux500-msp-i2s.%04x", | ||
714 | msp->id); | ||
715 | dev_dbg(&pdev->dev, "I2S device-name: '%s'\n", i2s_cont->name); | ||
716 | msp->i2s_cont = i2s_cont; | ||
717 | |||
718 | return 0; | ||
719 | |||
720 | err_i2s_cont: | ||
721 | iounmap(msp->registers); | ||
722 | |||
723 | err_res: | ||
724 | devm_kfree(&pdev->dev, msp); | ||
725 | |||
726 | return ret; | ||
727 | } | ||
728 | |||
729 | void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev, | ||
730 | struct ux500_msp *msp) | ||
731 | { | ||
732 | dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id); | ||
733 | |||
734 | device_unregister(&msp->i2s_cont->dev); | ||
735 | devm_kfree(&pdev->dev, msp->i2s_cont); | ||
736 | |||
737 | iounmap(msp->registers); | ||
738 | |||
739 | devm_kfree(&pdev->dev, msp); | ||
740 | } | ||
741 | |||
742 | MODULE_LICENSE("GPLv2"); | ||