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authorMark Brown <broonie@opensource.wolfsonmicro.com>2011-06-13 12:49:55 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-06-13 13:56:10 -0400
commit5bef44f9b4849d1c3af4ed2ea93061ff56e68cd7 (patch)
treeae5b6165d53888219729e3c193e556d2a71e3d65 /sound/soc/soc-cache.c
parentf0c4205b54113463ccb93c9ab064fc630c5c50bd (diff)
ASoC: Move register I/O code into a separate file
For clarity and to help ongoing refactoring in this area create a new file to contain the physical I/O functions, separating them out from the cache operations. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
Diffstat (limited to 'sound/soc/soc-cache.c')
-rw-r--r--sound/soc/soc-cache.c380
1 files changed, 0 insertions, 380 deletions
diff --git a/sound/soc/soc-cache.c b/sound/soc/soc-cache.c
index b88a61fd6de0..d9f8aded51f3 100644
--- a/sound/soc/soc-cache.c
+++ b/sound/soc/soc-cache.c
@@ -20,386 +20,6 @@
20 20
21#include <trace/events/asoc.h> 21#include <trace/events/asoc.h>
22 22
23#ifdef CONFIG_SPI_MASTER
24static int do_spi_write(void *control, const char *data, int len)
25{
26 struct spi_device *spi = control;
27 int ret;
28
29 ret = spi_write(spi, data, len);
30 if (ret < 0)
31 return ret;
32
33 return len;
34}
35#endif
36
37static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
38 unsigned int value, const void *data, int len)
39{
40 int ret;
41
42 if (!snd_soc_codec_volatile_register(codec, reg) &&
43 reg < codec->driver->reg_cache_size &&
44 !codec->cache_bypass) {
45 ret = snd_soc_cache_write(codec, reg, value);
46 if (ret < 0)
47 return -1;
48 }
49
50 if (codec->cache_only) {
51 codec->cache_sync = 1;
52 return 0;
53 }
54
55 ret = codec->hw_write(codec->control_data, data, len);
56 if (ret == len)
57 return 0;
58 if (ret < 0)
59 return ret;
60 else
61 return -EIO;
62}
63
64static unsigned int hw_read(struct snd_soc_codec *codec, unsigned int reg)
65{
66 int ret;
67 unsigned int val;
68
69 if (reg >= codec->driver->reg_cache_size ||
70 snd_soc_codec_volatile_register(codec, reg) ||
71 codec->cache_bypass) {
72 if (codec->cache_only)
73 return -1;
74
75 BUG_ON(!codec->hw_read);
76 return codec->hw_read(codec, reg);
77 }
78
79 ret = snd_soc_cache_read(codec, reg, &val);
80 if (ret < 0)
81 return -1;
82 return val;
83}
84
85static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
86 unsigned int value)
87{
88 u16 data;
89
90 data = cpu_to_be16((reg << 12) | (value & 0xffffff));
91
92 return do_hw_write(codec, reg, value, &data, 2);
93}
94
95static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
96 unsigned int value)
97{
98 u16 data;
99
100 data = cpu_to_be16((reg << 9) | (value & 0x1ff));
101
102 return do_hw_write(codec, reg, value, &data, 2);
103}
104
105static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
106 unsigned int value)
107{
108 u8 data[2];
109
110 reg &= 0xff;
111 data[0] = reg;
112 data[1] = value & 0xff;
113
114 return do_hw_write(codec, reg, value, data, 2);
115}
116
117static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
118 unsigned int value)
119{
120 u8 data[3];
121 u16 val = cpu_to_be16(value);
122
123 data[0] = reg;
124 memcpy(&data[1], &val, sizeof(val));
125
126 return do_hw_write(codec, reg, value, data, 3);
127}
128
129#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
130static unsigned int do_i2c_read(struct snd_soc_codec *codec,
131 void *reg, int reglen,
132 void *data, int datalen)
133{
134 struct i2c_msg xfer[2];
135 int ret;
136 struct i2c_client *client = codec->control_data;
137
138 /* Write register */
139 xfer[0].addr = client->addr;
140 xfer[0].flags = 0;
141 xfer[0].len = reglen;
142 xfer[0].buf = reg;
143
144 /* Read data */
145 xfer[1].addr = client->addr;
146 xfer[1].flags = I2C_M_RD;
147 xfer[1].len = datalen;
148 xfer[1].buf = data;
149
150 ret = i2c_transfer(client->adapter, xfer, 2);
151 if (ret == 2)
152 return 0;
153 else if (ret < 0)
154 return ret;
155 else
156 return -EIO;
157}
158#endif
159
160#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
161static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
162 unsigned int r)
163{
164 u8 reg = r;
165 u8 data;
166 int ret;
167
168 ret = do_i2c_read(codec, &reg, 1, &data, 1);
169 if (ret < 0)
170 return 0;
171 return data;
172}
173#else
174#define snd_soc_8_8_read_i2c NULL
175#endif
176
177#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
178static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
179 unsigned int r)
180{
181 u8 reg = r;
182 u16 data;
183 int ret;
184
185 ret = do_i2c_read(codec, &reg, 1, &data, 2);
186 if (ret < 0)
187 return 0;
188 return (data >> 8) | ((data & 0xff) << 8);
189}
190#else
191#define snd_soc_8_16_read_i2c NULL
192#endif
193
194#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
195static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
196 unsigned int r)
197{
198 u16 reg = r;
199 u8 data;
200 int ret;
201
202 ret = do_i2c_read(codec, &reg, 2, &data, 1);
203 if (ret < 0)
204 return 0;
205 return data;
206}
207#else
208#define snd_soc_16_8_read_i2c NULL
209#endif
210
211static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
212 unsigned int value)
213{
214 u8 data[3];
215 u16 rval = cpu_to_be16(reg);
216
217 memcpy(data, &rval, sizeof(rval));
218 data[2] = value;
219
220 return do_hw_write(codec, reg, value, data, 3);
221}
222
223#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
224static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
225 unsigned int r)
226{
227 u16 reg = cpu_to_be16(r);
228 u16 data;
229 int ret;
230
231 ret = do_i2c_read(codec, &reg, 2, &data, 2);
232 if (ret < 0)
233 return 0;
234 return be16_to_cpu(data);
235}
236#else
237#define snd_soc_16_16_read_i2c NULL
238#endif
239
240static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
241 unsigned int value)
242{
243 u16 data[2];
244
245 data[0] = cpu_to_be16(reg);
246 data[1] = cpu_to_be16(value);
247
248 return do_hw_write(codec, reg, value, data, sizeof(data));
249}
250
251/* Primitive bulk write support for soc-cache. The data pointed to by
252 * `data' needs to already be in the form the hardware expects
253 * including any leading register specific data. Any data written
254 * through this function will not go through the cache as it only
255 * handles writing to volatile or out of bounds registers.
256 */
257static int snd_soc_hw_bulk_write_raw(struct snd_soc_codec *codec, unsigned int reg,
258 const void *data, size_t len)
259{
260 int ret;
261
262 /* To ensure that we don't get out of sync with the cache, check
263 * whether the base register is volatile or if we've directly asked
264 * to bypass the cache. Out of bounds registers are considered
265 * volatile.
266 */
267 if (!codec->cache_bypass
268 && !snd_soc_codec_volatile_register(codec, reg)
269 && reg < codec->driver->reg_cache_size)
270 return -EINVAL;
271
272 switch (codec->control_type) {
273#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
274 case SND_SOC_I2C:
275 ret = i2c_master_send(codec->control_data, data, len);
276 break;
277#endif
278#if defined(CONFIG_SPI_MASTER)
279 case SND_SOC_SPI:
280 ret = spi_write(codec->control_data, data, len);
281 break;
282#endif
283 default:
284 BUG();
285 }
286
287 if (ret == len)
288 return 0;
289 if (ret < 0)
290 return ret;
291 else
292 return -EIO;
293}
294
295static struct {
296 int addr_bits;
297 int data_bits;
298 int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
299 unsigned int (*read)(struct snd_soc_codec *, unsigned int);
300 unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
301} io_types[] = {
302 {
303 .addr_bits = 4, .data_bits = 12,
304 .write = snd_soc_4_12_write,
305 },
306 {
307 .addr_bits = 7, .data_bits = 9,
308 .write = snd_soc_7_9_write,
309 },
310 {
311 .addr_bits = 8, .data_bits = 8,
312 .write = snd_soc_8_8_write,
313 .i2c_read = snd_soc_8_8_read_i2c,
314 },
315 {
316 .addr_bits = 8, .data_bits = 16,
317 .write = snd_soc_8_16_write,
318 .i2c_read = snd_soc_8_16_read_i2c,
319 },
320 {
321 .addr_bits = 16, .data_bits = 8,
322 .write = snd_soc_16_8_write,
323 .i2c_read = snd_soc_16_8_read_i2c,
324 },
325 {
326 .addr_bits = 16, .data_bits = 16,
327 .write = snd_soc_16_16_write,
328 .i2c_read = snd_soc_16_16_read_i2c,
329 },
330};
331
332/**
333 * snd_soc_codec_set_cache_io: Set up standard I/O functions.
334 *
335 * @codec: CODEC to configure.
336 * @addr_bits: Number of bits of register address data.
337 * @data_bits: Number of bits of data per register.
338 * @control: Control bus used.
339 *
340 * Register formats are frequently shared between many I2C and SPI
341 * devices. In order to promote code reuse the ASoC core provides
342 * some standard implementations of CODEC read and write operations
343 * which can be set up using this function.
344 *
345 * The caller is responsible for allocating and initialising the
346 * actual cache.
347 *
348 * Note that at present this code cannot be used by CODECs with
349 * volatile registers.
350 */
351int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
352 int addr_bits, int data_bits,
353 enum snd_soc_control_type control)
354{
355 int i;
356
357 for (i = 0; i < ARRAY_SIZE(io_types); i++)
358 if (io_types[i].addr_bits == addr_bits &&
359 io_types[i].data_bits == data_bits)
360 break;
361 if (i == ARRAY_SIZE(io_types)) {
362 printk(KERN_ERR
363 "No I/O functions for %d bit address %d bit data\n",
364 addr_bits, data_bits);
365 return -EINVAL;
366 }
367
368 codec->write = io_types[i].write;
369 codec->read = hw_read;
370 codec->bulk_write_raw = snd_soc_hw_bulk_write_raw;
371
372 switch (control) {
373 case SND_SOC_CUSTOM:
374 break;
375
376 case SND_SOC_I2C:
377#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
378 codec->hw_write = (hw_write_t)i2c_master_send;
379#endif
380 if (io_types[i].i2c_read)
381 codec->hw_read = io_types[i].i2c_read;
382
383 codec->control_data = container_of(codec->dev,
384 struct i2c_client,
385 dev);
386 break;
387
388 case SND_SOC_SPI:
389#ifdef CONFIG_SPI_MASTER
390 codec->hw_write = do_spi_write;
391#endif
392
393 codec->control_data = container_of(codec->dev,
394 struct spi_device,
395 dev);
396 break;
397 }
398
399 return 0;
400}
401EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
402
403static bool snd_soc_set_cache_val(void *base, unsigned int idx, 23static bool snd_soc_set_cache_val(void *base, unsigned int idx,
404 unsigned int val, unsigned int word_size) 24 unsigned int val, unsigned int word_size)
405{ 25{
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