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authorGraeme Gregory <graeme@openmoko.com>2008-01-10 08:44:24 -0500
committerJaroslav Kysela <perex@perex.cz>2008-01-31 11:29:51 -0500
commit96d90e19307ce590097295026a2e1b36618ddd01 (patch)
tree8fb6dea26f715346f32a26639b295e692c3c3a95 /sound/soc/s3c24xx
parent2d6a4ac9eeb8e8eb0343a2c761b2c132957d2b71 (diff)
[ALSA] soc - Reinitialise DMA on every resume
This one changes the DMA initialisation as it turns out the DMA driver in s3c24xx doesnt store registers between suspend/resume so you have to re-initialise the channels on every resume. Signed-off-by: Graeme Gregory <graeme@openmoko.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
Diffstat (limited to 'sound/soc/s3c24xx')
-rw-r--r--sound/soc/s3c24xx/s3c24xx-pcm.c48
1 files changed, 25 insertions, 23 deletions
diff --git a/sound/soc/s3c24xx/s3c24xx-pcm.c b/sound/soc/s3c24xx/s3c24xx-pcm.c
index 290dcf12b5ae..29a6c82f873a 100644
--- a/sound/soc/s3c24xx/s3c24xx-pcm.c
+++ b/sound/soc/s3c24xx/s3c24xx-pcm.c
@@ -48,7 +48,9 @@ static const struct snd_pcm_hardware s3c24xx_pcm_hardware = {
48 .info = SNDRV_PCM_INFO_INTERLEAVED | 48 .info = SNDRV_PCM_INFO_INTERLEAVED |
49 SNDRV_PCM_INFO_BLOCK_TRANSFER | 49 SNDRV_PCM_INFO_BLOCK_TRANSFER |
50 SNDRV_PCM_INFO_MMAP | 50 SNDRV_PCM_INFO_MMAP |
51 SNDRV_PCM_INFO_MMAP_VALID, 51 SNDRV_PCM_INFO_MMAP_VALID |
52 SNDRV_PCM_INFO_PAUSE |
53 SNDRV_PCM_INFO_RESUME,
52 .formats = SNDRV_PCM_FMTBIT_S16_LE | 54 .formats = SNDRV_PCM_FMTBIT_S16_LE |
53 SNDRV_PCM_FMTBIT_U16_LE | 55 SNDRV_PCM_FMTBIT_U16_LE |
54 SNDRV_PCM_FMTBIT_U8 | 56 SNDRV_PCM_FMTBIT_U8 |
@@ -175,28 +177,6 @@ static int s3c24xx_pcm_hw_params(struct snd_pcm_substream *substream,
175 } 177 }
176 } 178 }
177 179
178 /* channel needs configuring for mem=>device, increment memory addr,
179 * sync to pclk, half-word transfers to the IIS-FIFO. */
180 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
181 s3c2410_dma_devconfig(prtd->params->channel,
182 S3C2410_DMASRC_MEM, S3C2410_DISRCC_INC |
183 S3C2410_DISRCC_APB, prtd->params->dma_addr);
184
185 s3c2410_dma_config(prtd->params->channel,
186 prtd->params->dma_size,
187 S3C2410_DCON_SYNC_PCLK |
188 S3C2410_DCON_HANDSHAKE);
189 } else {
190 s3c2410_dma_config(prtd->params->channel,
191 prtd->params->dma_size,
192 S3C2410_DCON_HANDSHAKE |
193 S3C2410_DCON_SYNC_PCLK);
194
195 s3c2410_dma_devconfig(prtd->params->channel,
196 S3C2410_DMASRC_HW, 0x3,
197 prtd->params->dma_addr);
198 }
199
200 s3c2410_dma_set_buffdone_fn(prtd->params->channel, 180 s3c2410_dma_set_buffdone_fn(prtd->params->channel,
201 s3c24xx_audio_buffdone); 181 s3c24xx_audio_buffdone);
202 182
@@ -245,6 +225,28 @@ static int s3c24xx_pcm_prepare(struct snd_pcm_substream *substream)
245 if (!prtd->params) 225 if (!prtd->params)
246 return 0; 226 return 0;
247 227
228 /* channel needs configuring for mem=>device, increment memory addr,
229 * sync to pclk, half-word transfers to the IIS-FIFO. */
230 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
231 s3c2410_dma_devconfig(prtd->params->channel,
232 S3C2410_DMASRC_MEM, S3C2410_DISRCC_INC |
233 S3C2410_DISRCC_APB, prtd->params->dma_addr);
234
235 s3c2410_dma_config(prtd->params->channel,
236 prtd->params->dma_size,
237 S3C2410_DCON_SYNC_PCLK |
238 S3C2410_DCON_HANDSHAKE);
239 } else {
240 s3c2410_dma_config(prtd->params->channel,
241 prtd->params->dma_size,
242 S3C2410_DCON_HANDSHAKE |
243 S3C2410_DCON_SYNC_PCLK);
244
245 s3c2410_dma_devconfig(prtd->params->channel,
246 S3C2410_DMASRC_HW, 0x3,
247 prtd->params->dma_addr);
248 }
249
248 /* flush the DMA channel */ 250 /* flush the DMA channel */
249 s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_FLUSH); 251 s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_FLUSH);
250 prtd->dma_loaded = 0; 252 prtd->dma_loaded = 0;