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authorJorge Eduardo Candelaria <jorge.candelaria@ti.com>2010-03-18 21:45:41 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-03-19 07:14:39 -0400
commit9fc71e8f586efc99472337a8b089a4915877b4b8 (patch)
tree257af5dd65e2197c0763e5a13e63a66cf6825c9d /sound/soc/omap/mcpdm.c
parent6a1c7b7e2ea3ca5f6ae73154c4b72755d262c9e0 (diff)
ASoC: McPDM: Use tabs for indentation
Indentation in initial support for McPDM driver was converted to spaces. Use tabs to comply with open source coding-style. Signed-off-by: Jorge Eduardo Candelaria <jorge.candelaria@ti.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/omap/mcpdm.c')
-rw-r--r--sound/soc/omap/mcpdm.c548
1 files changed, 274 insertions, 274 deletions
diff --git a/sound/soc/omap/mcpdm.c b/sound/soc/omap/mcpdm.c
index ad8df6cfae88..479d3b6306d7 100644
--- a/sound/soc/omap/mcpdm.c
+++ b/sound/soc/omap/mcpdm.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * mcpdm.c -- McPDM interface driver 2 * mcpdm.c -- McPDM interface driver
3 * 3 *
4 * Author: Jorge Eduardo Candelaria <x0107209@ti.com> 4 * Author: Jorge Eduardo Candelaria <x0107209@ti.com>
5 * Copyright (C) 2009 - Texas Instruments, Inc. 5 * Copyright (C) 2009 - Texas Instruments, Inc.
@@ -38,46 +38,46 @@ static struct omap_mcpdm *mcpdm;
38 38
39static inline void omap_mcpdm_write(u16 reg, u32 val) 39static inline void omap_mcpdm_write(u16 reg, u32 val)
40{ 40{
41 __raw_writel(val, mcpdm->io_base + reg); 41 __raw_writel(val, mcpdm->io_base + reg);
42} 42}
43 43
44static inline int omap_mcpdm_read(u16 reg) 44static inline int omap_mcpdm_read(u16 reg)
45{ 45{
46 return __raw_readl(mcpdm->io_base + reg); 46 return __raw_readl(mcpdm->io_base + reg);
47} 47}
48 48
49static void omap_mcpdm_reg_dump(void) 49static void omap_mcpdm_reg_dump(void)
50{ 50{
51 dev_dbg(mcpdm->dev, "***********************\n"); 51 dev_dbg(mcpdm->dev, "***********************\n");
52 dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n", 52 dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
53 omap_mcpdm_read(MCPDM_IRQSTATUS_RAW)); 53 omap_mcpdm_read(MCPDM_IRQSTATUS_RAW));
54 dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n", 54 dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
55 omap_mcpdm_read(MCPDM_IRQSTATUS)); 55 omap_mcpdm_read(MCPDM_IRQSTATUS));
56 dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n", 56 dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
57 omap_mcpdm_read(MCPDM_IRQENABLE_SET)); 57 omap_mcpdm_read(MCPDM_IRQENABLE_SET));
58 dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n", 58 dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
59 omap_mcpdm_read(MCPDM_IRQENABLE_CLR)); 59 omap_mcpdm_read(MCPDM_IRQENABLE_CLR));
60 dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n", 60 dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
61 omap_mcpdm_read(MCPDM_IRQWAKE_EN)); 61 omap_mcpdm_read(MCPDM_IRQWAKE_EN));
62 dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n", 62 dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
63 omap_mcpdm_read(MCPDM_DMAENABLE_SET)); 63 omap_mcpdm_read(MCPDM_DMAENABLE_SET));
64 dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n", 64 dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
65 omap_mcpdm_read(MCPDM_DMAENABLE_CLR)); 65 omap_mcpdm_read(MCPDM_DMAENABLE_CLR));
66 dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n", 66 dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
67 omap_mcpdm_read(MCPDM_DMAWAKEEN)); 67 omap_mcpdm_read(MCPDM_DMAWAKEEN));
68 dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n", 68 dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
69 omap_mcpdm_read(MCPDM_CTRL)); 69 omap_mcpdm_read(MCPDM_CTRL));
70 dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n", 70 dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
71 omap_mcpdm_read(MCPDM_DN_DATA)); 71 omap_mcpdm_read(MCPDM_DN_DATA));
72 dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n", 72 dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
73 omap_mcpdm_read(MCPDM_UP_DATA)); 73 omap_mcpdm_read(MCPDM_UP_DATA));
74 dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n", 74 dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
75 omap_mcpdm_read(MCPDM_FIFO_CTRL_DN)); 75 omap_mcpdm_read(MCPDM_FIFO_CTRL_DN));
76 dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n", 76 dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
77 omap_mcpdm_read(MCPDM_FIFO_CTRL_UP)); 77 omap_mcpdm_read(MCPDM_FIFO_CTRL_UP));
78 dev_dbg(mcpdm->dev, "DN_OFFSET: 0x%04x\n", 78 dev_dbg(mcpdm->dev, "DN_OFFSET: 0x%04x\n",
79 omap_mcpdm_read(MCPDM_DN_OFFSET)); 79 omap_mcpdm_read(MCPDM_DN_OFFSET));
80 dev_dbg(mcpdm->dev, "***********************\n"); 80 dev_dbg(mcpdm->dev, "***********************\n");
81} 81}
82 82
83/* 83/*
@@ -86,26 +86,26 @@ static void omap_mcpdm_reg_dump(void)
86 */ 86 */
87static void omap_mcpdm_reset_capture(int reset) 87static void omap_mcpdm_reset_capture(int reset)
88{ 88{
89 int ctrl = omap_mcpdm_read(MCPDM_CTRL); 89 int ctrl = omap_mcpdm_read(MCPDM_CTRL);
90 90
91 if (reset) 91 if (reset)
92 ctrl |= SW_UP_RST; 92 ctrl |= SW_UP_RST;
93 else 93 else
94 ctrl &= ~SW_UP_RST; 94 ctrl &= ~SW_UP_RST;
95 95
96 omap_mcpdm_write(MCPDM_CTRL, ctrl); 96 omap_mcpdm_write(MCPDM_CTRL, ctrl);
97} 97}
98 98
99static void omap_mcpdm_reset_playback(int reset) 99static void omap_mcpdm_reset_playback(int reset)
100{ 100{
101 int ctrl = omap_mcpdm_read(MCPDM_CTRL); 101 int ctrl = omap_mcpdm_read(MCPDM_CTRL);
102 102
103 if (reset) 103 if (reset)
104 ctrl |= SW_DN_RST; 104 ctrl |= SW_DN_RST;
105 else 105 else
106 ctrl &= ~SW_DN_RST; 106 ctrl &= ~SW_DN_RST;
107 107
108 omap_mcpdm_write(MCPDM_CTRL, ctrl); 108 omap_mcpdm_write(MCPDM_CTRL, ctrl);
109} 109}
110 110
111/* 111/*
@@ -114,14 +114,14 @@ static void omap_mcpdm_reset_playback(int reset)
114 */ 114 */
115void omap_mcpdm_start(int stream) 115void omap_mcpdm_start(int stream)
116{ 116{
117 int ctrl = omap_mcpdm_read(MCPDM_CTRL); 117 int ctrl = omap_mcpdm_read(MCPDM_CTRL);
118 118
119 if (stream) 119 if (stream)
120 ctrl |= mcpdm->up_channels; 120 ctrl |= mcpdm->up_channels;
121 else 121 else
122 ctrl |= mcpdm->dn_channels; 122 ctrl |= mcpdm->dn_channels;
123 123
124 omap_mcpdm_write(MCPDM_CTRL, ctrl); 124 omap_mcpdm_write(MCPDM_CTRL, ctrl);
125} 125}
126 126
127/* 127/*
@@ -130,14 +130,14 @@ void omap_mcpdm_start(int stream)
130 */ 130 */
131void omap_mcpdm_stop(int stream) 131void omap_mcpdm_stop(int stream)
132{ 132{
133 int ctrl = omap_mcpdm_read(MCPDM_CTRL); 133 int ctrl = omap_mcpdm_read(MCPDM_CTRL);
134 134
135 if (stream) 135 if (stream)
136 ctrl &= ~mcpdm->up_channels; 136 ctrl &= ~mcpdm->up_channels;
137 else 137 else
138 ctrl &= ~mcpdm->dn_channels; 138 ctrl &= ~mcpdm->dn_channels;
139 139
140 omap_mcpdm_write(MCPDM_CTRL, ctrl); 140 omap_mcpdm_write(MCPDM_CTRL, ctrl);
141} 141}
142 142
143/* 143/*
@@ -146,38 +146,38 @@ void omap_mcpdm_stop(int stream)
146 */ 146 */
147int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink) 147int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink)
148{ 148{
149 int irq_mask = 0; 149 int irq_mask = 0;
150 int ctrl; 150 int ctrl;
151 151
152 if (!uplink) 152 if (!uplink)
153 return -EINVAL; 153 return -EINVAL;
154 154
155 mcpdm->uplink = uplink; 155 mcpdm->uplink = uplink;
156 156
157 /* Enable irq request generation */ 157 /* Enable irq request generation */
158 irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK; 158 irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
159 omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask); 159 omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
160 160
161 /* Configure uplink threshold */ 161 /* Configure uplink threshold */
162 if (uplink->threshold > UP_THRES_MAX) 162 if (uplink->threshold > UP_THRES_MAX)
163 uplink->threshold = UP_THRES_MAX; 163 uplink->threshold = UP_THRES_MAX;
164 164
165 omap_mcpdm_write(MCPDM_FIFO_CTRL_UP, uplink->threshold); 165 omap_mcpdm_write(MCPDM_FIFO_CTRL_UP, uplink->threshold);
166 166
167 /* Configure DMA controller */ 167 /* Configure DMA controller */
168 omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_UP_ENABLE); 168 omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_UP_ENABLE);
169 169
170 /* Set pdm out format */ 170 /* Set pdm out format */
171 ctrl = omap_mcpdm_read(MCPDM_CTRL); 171 ctrl = omap_mcpdm_read(MCPDM_CTRL);
172 ctrl &= ~PDMOUTFORMAT; 172 ctrl &= ~PDMOUTFORMAT;
173 ctrl |= uplink->format & PDMOUTFORMAT; 173 ctrl |= uplink->format & PDMOUTFORMAT;
174 174
175 /* Uplink channels */ 175 /* Uplink channels */
176 mcpdm->up_channels = uplink->channels & (PDM_UP_MASK | PDM_STATUS_MASK); 176 mcpdm->up_channels = uplink->channels & (PDM_UP_MASK | PDM_STATUS_MASK);
177 177
178 omap_mcpdm_write(MCPDM_CTRL, ctrl); 178 omap_mcpdm_write(MCPDM_CTRL, ctrl);
179 179
180 return 0; 180 return 0;
181} 181}
182 182
183/* 183/*
@@ -186,38 +186,38 @@ int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink)
186 */ 186 */
187int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink) 187int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink)
188{ 188{
189 int irq_mask = 0; 189 int irq_mask = 0;
190 int ctrl; 190 int ctrl;
191 191
192 if (!downlink) 192 if (!downlink)
193 return -EINVAL; 193 return -EINVAL;
194 194
195 mcpdm->downlink = downlink; 195 mcpdm->downlink = downlink;
196 196
197 /* Enable irq request generation */ 197 /* Enable irq request generation */
198 irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK; 198 irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
199 omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask); 199 omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
200 200
201 /* Configure uplink threshold */ 201 /* Configure uplink threshold */
202 if (downlink->threshold > DN_THRES_MAX) 202 if (downlink->threshold > DN_THRES_MAX)
203 downlink->threshold = DN_THRES_MAX; 203 downlink->threshold = DN_THRES_MAX;
204 204
205 omap_mcpdm_write(MCPDM_FIFO_CTRL_DN, downlink->threshold); 205 omap_mcpdm_write(MCPDM_FIFO_CTRL_DN, downlink->threshold);
206 206
207 /* Enable DMA request generation */ 207 /* Enable DMA request generation */
208 omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_DN_ENABLE); 208 omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_DN_ENABLE);
209 209
210 /* Set pdm out format */ 210 /* Set pdm out format */
211 ctrl = omap_mcpdm_read(MCPDM_CTRL); 211 ctrl = omap_mcpdm_read(MCPDM_CTRL);
212 ctrl &= ~PDMOUTFORMAT; 212 ctrl &= ~PDMOUTFORMAT;
213 ctrl |= downlink->format & PDMOUTFORMAT; 213 ctrl |= downlink->format & PDMOUTFORMAT;
214 214
215 /* Downlink channels */ 215 /* Downlink channels */
216 mcpdm->dn_channels = downlink->channels & (PDM_DN_MASK | PDM_CMD_MASK); 216 mcpdm->dn_channels = downlink->channels & (PDM_DN_MASK | PDM_CMD_MASK);
217 217
218 omap_mcpdm_write(MCPDM_CTRL, ctrl); 218 omap_mcpdm_write(MCPDM_CTRL, ctrl);
219 219
220 return 0; 220 return 0;
221} 221}
222 222
223/* 223/*
@@ -226,24 +226,24 @@ int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink)
226 */ 226 */
227int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink) 227int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink)
228{ 228{
229 int irq_mask = 0; 229 int irq_mask = 0;
230 230
231 if (!uplink) 231 if (!uplink)
232 return -EINVAL; 232 return -EINVAL;
233 233
234 /* Disable irq request generation */ 234 /* Disable irq request generation */
235 irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK; 235 irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
236 omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask); 236 omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
237 237
238 /* Disable DMA request generation */ 238 /* Disable DMA request generation */
239 omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_UP_ENABLE); 239 omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_UP_ENABLE);
240 240
241 /* Clear Downlink channels */ 241 /* Clear Downlink channels */
242 mcpdm->up_channels = 0; 242 mcpdm->up_channels = 0;
243 243
244 mcpdm->uplink = NULL; 244 mcpdm->uplink = NULL;
245 245
246 return 0; 246 return 0;
247} 247}
248 248
249/* 249/*
@@ -252,124 +252,124 @@ int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink)
252 */ 252 */
253int omap_mcpdm_playback_close(struct omap_mcpdm_link *downlink) 253int omap_mcpdm_playback_close(struct omap_mcpdm_link *downlink)
254{ 254{
255 int irq_mask = 0; 255 int irq_mask = 0;
256 256
257 if (!downlink) 257 if (!downlink)
258 return -EINVAL; 258 return -EINVAL;
259 259
260 /* Disable irq request generation */ 260 /* Disable irq request generation */
261 irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK; 261 irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
262 omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask); 262 omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
263 263
264 /* Disable DMA request generation */ 264 /* Disable DMA request generation */
265 omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_DN_ENABLE); 265 omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_DN_ENABLE);
266 266
267 /* clear Downlink channels */ 267 /* clear Downlink channels */
268 mcpdm->dn_channels = 0; 268 mcpdm->dn_channels = 0;
269 269
270 mcpdm->downlink = NULL; 270 mcpdm->downlink = NULL;
271 271
272 return 0; 272 return 0;
273} 273}
274 274
275static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id) 275static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
276{ 276{
277 struct omap_mcpdm *mcpdm_irq = dev_id; 277 struct omap_mcpdm *mcpdm_irq = dev_id;
278 int irq_status; 278 int irq_status;
279 279
280 irq_status = omap_mcpdm_read(MCPDM_IRQSTATUS); 280 irq_status = omap_mcpdm_read(MCPDM_IRQSTATUS);
281 281
282 /* Acknowledge irq event */ 282 /* Acknowledge irq event */
283 omap_mcpdm_write(MCPDM_IRQSTATUS, irq_status); 283 omap_mcpdm_write(MCPDM_IRQSTATUS, irq_status);
284 284
285 if (irq & MCPDM_DN_IRQ_FULL) { 285 if (irq & MCPDM_DN_IRQ_FULL) {
286 dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status); 286 dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
287 omap_mcpdm_reset_playback(1); 287 omap_mcpdm_reset_playback(1);
288 omap_mcpdm_playback_open(mcpdm_irq->downlink); 288 omap_mcpdm_playback_open(mcpdm_irq->downlink);
289 omap_mcpdm_reset_playback(0); 289 omap_mcpdm_reset_playback(0);
290 } 290 }
291 291
292 if (irq & MCPDM_DN_IRQ_EMPTY) { 292 if (irq & MCPDM_DN_IRQ_EMPTY) {
293 dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status); 293 dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
294 omap_mcpdm_reset_playback(1); 294 omap_mcpdm_reset_playback(1);
295 omap_mcpdm_playback_open(mcpdm_irq->downlink); 295 omap_mcpdm_playback_open(mcpdm_irq->downlink);
296 omap_mcpdm_reset_playback(0); 296 omap_mcpdm_reset_playback(0);
297 } 297 }
298 298
299 if (irq & MCPDM_DN_IRQ) { 299 if (irq & MCPDM_DN_IRQ) {
300 dev_dbg(mcpdm_irq->dev, "DN write request\n"); 300 dev_dbg(mcpdm_irq->dev, "DN write request\n");
301 } 301 }
302 302
303 if (irq & MCPDM_UP_IRQ_FULL) { 303 if (irq & MCPDM_UP_IRQ_FULL) {
304 dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status); 304 dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
305 omap_mcpdm_reset_capture(1); 305 omap_mcpdm_reset_capture(1);
306 omap_mcpdm_capture_open(mcpdm_irq->uplink); 306 omap_mcpdm_capture_open(mcpdm_irq->uplink);
307 omap_mcpdm_reset_capture(0); 307 omap_mcpdm_reset_capture(0);
308 } 308 }
309 309
310 if (irq & MCPDM_UP_IRQ_EMPTY) { 310 if (irq & MCPDM_UP_IRQ_EMPTY) {
311 dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status); 311 dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
312 omap_mcpdm_reset_capture(1); 312 omap_mcpdm_reset_capture(1);
313 omap_mcpdm_capture_open(mcpdm_irq->uplink); 313 omap_mcpdm_capture_open(mcpdm_irq->uplink);
314 omap_mcpdm_reset_capture(0); 314 omap_mcpdm_reset_capture(0);
315 } 315 }
316 316
317 if (irq & MCPDM_UP_IRQ) { 317 if (irq & MCPDM_UP_IRQ) {
318 dev_dbg(mcpdm_irq->dev, "UP write request\n"); 318 dev_dbg(mcpdm_irq->dev, "UP write request\n");
319 } 319 }
320 320
321 return IRQ_HANDLED; 321 return IRQ_HANDLED;
322} 322}
323 323
324int omap_mcpdm_request(void) 324int omap_mcpdm_request(void)
325{ 325{
326 int ret; 326 int ret;
327 327
328 clk_enable(mcpdm->clk); 328 clk_enable(mcpdm->clk);
329 329
330 spin_lock(&mcpdm->lock); 330 spin_lock(&mcpdm->lock);
331 331
332 if (!mcpdm->free) { 332 if (!mcpdm->free) {
333 dev_err(mcpdm->dev, "McPDM interface is in use\n"); 333 dev_err(mcpdm->dev, "McPDM interface is in use\n");
334 spin_unlock(&mcpdm->lock); 334 spin_unlock(&mcpdm->lock);
335 ret = -EBUSY; 335 ret = -EBUSY;
336 goto err; 336 goto err;
337 } 337 }
338 mcpdm->free = 0; 338 mcpdm->free = 0;
339 339
340 spin_unlock(&mcpdm->lock); 340 spin_unlock(&mcpdm->lock);
341 341
342 /* Disable lines while request is ongoing */ 342 /* Disable lines while request is ongoing */
343 omap_mcpdm_write(MCPDM_CTRL, 0x00); 343 omap_mcpdm_write(MCPDM_CTRL, 0x00);
344 344
345 ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler, 345 ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
346 0, "McPDM", (void *)mcpdm); 346 0, "McPDM", (void *)mcpdm);
347 if (ret) { 347 if (ret) {
348 dev_err(mcpdm->dev, "Request for McPDM IRQ failed\n"); 348 dev_err(mcpdm->dev, "Request for McPDM IRQ failed\n");
349 goto err; 349 goto err;
350 } 350 }
351 351
352 return 0; 352 return 0;
353 353
354err: 354err:
355 clk_disable(mcpdm->clk); 355 clk_disable(mcpdm->clk);
356 return ret; 356 return ret;
357} 357}
358 358
359void omap_mcpdm_free(void) 359void omap_mcpdm_free(void)
360{ 360{
361 spin_lock(&mcpdm->lock); 361 spin_lock(&mcpdm->lock);
362 if (mcpdm->free) { 362 if (mcpdm->free) {
363 dev_err(mcpdm->dev, "McPDM interface is already free\n"); 363 dev_err(mcpdm->dev, "McPDM interface is already free\n");
364 spin_unlock(&mcpdm->lock); 364 spin_unlock(&mcpdm->lock);
365 return; 365 return;
366 } 366 }
367 mcpdm->free = 1; 367 mcpdm->free = 1;
368 spin_unlock(&mcpdm->lock); 368 spin_unlock(&mcpdm->lock);
369 369
370 clk_disable(mcpdm->clk); 370 clk_disable(mcpdm->clk);
371 371
372 free_irq(mcpdm->irq, (void *)mcpdm); 372 free_irq(mcpdm->irq, (void *)mcpdm);
373} 373}
374 374
375/* Enable/disable DC offset cancelation for the analog 375/* Enable/disable DC offset cancelation for the analog
@@ -377,108 +377,108 @@ void omap_mcpdm_free(void)
377 */ 377 */
378int omap_mcpdm_set_offset(int offset1, int offset2) 378int omap_mcpdm_set_offset(int offset1, int offset2)
379{ 379{
380 int offset; 380 int offset;
381 381
382 if ((offset1 > DN_OFST_MAX) || (offset2 > DN_OFST_MAX)) 382 if ((offset1 > DN_OFST_MAX) || (offset2 > DN_OFST_MAX))
383 return -EINVAL; 383 return -EINVAL;
384 384
385 offset = (offset1 << DN_OFST_RX1) | (offset2 << DN_OFST_RX2); 385 offset = (offset1 << DN_OFST_RX1) | (offset2 << DN_OFST_RX2);
386 386
387 /* offset cancellation for channel 1 */ 387 /* offset cancellation for channel 1 */
388 if (offset1) 388 if (offset1)
389 offset |= DN_OFST_RX1_EN; 389 offset |= DN_OFST_RX1_EN;
390 else 390 else
391 offset &= ~DN_OFST_RX1_EN; 391 offset &= ~DN_OFST_RX1_EN;
392 392
393 /* offset cancellation for channel 2 */ 393 /* offset cancellation for channel 2 */
394 if (offset2) 394 if (offset2)
395 offset |= DN_OFST_RX2_EN; 395 offset |= DN_OFST_RX2_EN;
396 else 396 else
397 offset &= ~DN_OFST_RX2_EN; 397 offset &= ~DN_OFST_RX2_EN;
398 398
399 omap_mcpdm_write(MCPDM_DN_OFFSET, offset); 399 omap_mcpdm_write(MCPDM_DN_OFFSET, offset);
400 400
401 return 0; 401 return 0;
402} 402}
403 403
404static int __devinit omap_mcpdm_probe(struct platform_device *pdev) 404static int __devinit omap_mcpdm_probe(struct platform_device *pdev)
405{ 405{
406 struct resource *res; 406 struct resource *res;
407 int ret = 0; 407 int ret = 0;
408 408
409 mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL); 409 mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
410 if (!mcpdm) { 410 if (!mcpdm) {
411 ret = -ENOMEM; 411 ret = -ENOMEM;
412 goto exit; 412 goto exit;
413 } 413 }
414 414
415 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 415 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
416 if (res == NULL) { 416 if (res == NULL) {
417 dev_err(&pdev->dev, "no resource\n"); 417 dev_err(&pdev->dev, "no resource\n");
418 goto err_resource; 418 goto err_resource;
419 } 419 }
420 420
421 spin_lock_init(&mcpdm->lock); 421 spin_lock_init(&mcpdm->lock);
422 mcpdm->free = 1; 422 mcpdm->free = 1;
423 mcpdm->io_base = ioremap(res->start, resource_size(res)); 423 mcpdm->io_base = ioremap(res->start, resource_size(res));
424 if (!mcpdm->io_base) { 424 if (!mcpdm->io_base) {
425 ret = -ENOMEM; 425 ret = -ENOMEM;
426 goto err_resource; 426 goto err_resource;
427 } 427 }
428 428
429 mcpdm->irq = platform_get_irq(pdev, 0); 429 mcpdm->irq = platform_get_irq(pdev, 0);
430 430
431 mcpdm->clk = clk_get(&pdev->dev, "pdm_ck"); 431 mcpdm->clk = clk_get(&pdev->dev, "pdm_ck");
432 if (IS_ERR(mcpdm->clk)) { 432 if (IS_ERR(mcpdm->clk)) {
433 ret = PTR_ERR(mcpdm->clk); 433 ret = PTR_ERR(mcpdm->clk);
434 dev_err(&pdev->dev, "unable to get pdm_ck: %d\n", ret); 434 dev_err(&pdev->dev, "unable to get pdm_ck: %d\n", ret);
435 goto err_clk; 435 goto err_clk;
436 } 436 }
437 437
438 mcpdm->dev = &pdev->dev; 438 mcpdm->dev = &pdev->dev;
439 platform_set_drvdata(pdev, mcpdm); 439 platform_set_drvdata(pdev, mcpdm);
440 440
441 return 0; 441 return 0;
442 442
443err_clk: 443err_clk:
444 iounmap(mcpdm->io_base); 444 iounmap(mcpdm->io_base);
445err_resource: 445err_resource:
446 kfree(mcpdm); 446 kfree(mcpdm);
447exit: 447exit:
448 return ret; 448 return ret;
449} 449}
450 450
451static int __devexit omap_mcpdm_remove(struct platform_device *pdev) 451static int __devexit omap_mcpdm_remove(struct platform_device *pdev)
452{ 452{
453 struct omap_mcpdm *mcpdm_ptr = platform_get_drvdata(pdev); 453 struct omap_mcpdm *mcpdm_ptr = platform_get_drvdata(pdev);
454 454
455 platform_set_drvdata(pdev, NULL); 455 platform_set_drvdata(pdev, NULL);
456 456
457 clk_put(mcpdm_ptr->clk); 457 clk_put(mcpdm_ptr->clk);
458 458
459 iounmap(mcpdm_ptr->io_base); 459 iounmap(mcpdm_ptr->io_base);
460 460
461 mcpdm_ptr->clk = NULL; 461 mcpdm_ptr->clk = NULL;
462 mcpdm_ptr->free = 0; 462 mcpdm_ptr->free = 0;
463 mcpdm_ptr->dev = NULL; 463 mcpdm_ptr->dev = NULL;
464 464
465 kfree(mcpdm_ptr); 465 kfree(mcpdm_ptr);
466 466
467 return 0; 467 return 0;
468} 468}
469 469
470static struct platform_driver omap_mcpdm_driver = { 470static struct platform_driver omap_mcpdm_driver = {
471 .probe = omap_mcpdm_probe, 471 .probe = omap_mcpdm_probe,
472 .remove = __devexit_p(omap_mcpdm_remove), 472 .remove = __devexit_p(omap_mcpdm_remove),
473 .driver = { 473 .driver = {
474 .name = "omap-mcpdm", 474 .name = "omap-mcpdm",
475 }, 475 },
476}; 476};
477 477
478static struct platform_device *omap_mcpdm_device; 478static struct platform_device *omap_mcpdm_device;
479 479
480static int __init omap_mcpdm_init(void) 480static int __init omap_mcpdm_init(void)
481{ 481{
482 return platform_driver_register(&omap_mcpdm_driver); 482 return platform_driver_register(&omap_mcpdm_driver);
483} 483}
484arch_initcall(omap_mcpdm_init); 484arch_initcall(omap_mcpdm_init);