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authorNicolin Chen <Guangyu.Chen@freescale.com>2014-07-23 07:23:40 -0400
committerMark Brown <broonie@linaro.org>2014-07-25 13:52:35 -0400
commita3fdc6749edf4dcb07df3a10bbdd9850ed5fd01a (patch)
tree6ce849c50cb1c7bda1875b87d610155153c621a3 /sound/soc/fsl
parentc44b56af9ca3a6f135d8f22b9a240f53909b371e (diff)
ASoC: fsl_sai: Improve enable flow in fsl_sai_trigger()
The previous enable flow: 1, Enable TE&RE (SAI starts to consume tx FIFO and feed rx FIFO) 2, Mask IRQ of Tx/Rx to enable its interrupt. 3, Enable DMA request of Tx/Rx. As this flow would enable DMA request later than TERE, the Tx FIFO would be easily emptied into underrun while Rx FIFO would be easily stuffed into overrun due to the delayed DMA transfering. This issue happened merely occational before the patch 'ASoC: fsl_sai: Reset FIFOs after disabling TE/RE' because there were useless data remaining in the FIFO for the gap. However, it manifested after FIFO reset's implemented. After this patch, the new flow: 1, Enable DMA request of Tx/Rx. 2, Enable TE&RE (SAI starts to consume tx FIFO and feed rx FIFO) 3, Mask IRQ of Tx/Rx to enable its interrupt. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'sound/soc/fsl')
-rw-r--r--sound/soc/fsl/fsl_sai.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index a79a9b0c08fd..364410be3c4e 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -346,6 +346,9 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
346 case SNDRV_PCM_TRIGGER_START: 346 case SNDRV_PCM_TRIGGER_START:
347 case SNDRV_PCM_TRIGGER_RESUME: 347 case SNDRV_PCM_TRIGGER_RESUME:
348 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 348 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
349 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
350 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
351
349 regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 352 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
350 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 353 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
351 regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 354 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
@@ -353,8 +356,6 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
353 356
354 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), 357 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
355 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 358 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
356 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
357 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
358 break; 359 break;
359 case SNDRV_PCM_TRIGGER_STOP: 360 case SNDRV_PCM_TRIGGER_STOP:
360 case SNDRV_PCM_TRIGGER_SUSPEND: 361 case SNDRV_PCM_TRIGGER_SUSPEND: