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authorChaithrika U S <chaithrika@ti.com>2009-09-15 18:13:29 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2009-09-18 10:08:31 -0400
commit0c31cf3e4af79ea18bbd365b07ef0de207673894 (patch)
tree883f469e229f49c97e159e397a00082589ca2cfb /sound/soc/davinci
parentad80efc469f56d41f3f4adc1b2c86bf65689ebeb (diff)
ASoC: DaVinci: Fixes to McASP configuration
McASP register settings are not correct for DSP mode of operation. There is a channel swap initally. This patch provides fixes to the register values for proper working. Tested on DA830/OMAP-L137 EVM, DM6467 EVM. Signed-off-by: Chaithrika U S <chaithrika@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/davinci')
-rw-r--r--sound/soc/davinci/davinci-mcasp.c24
1 files changed, 22 insertions, 2 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index eca22d7829d2..7a06c0a86665 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -512,34 +512,49 @@ static int davinci_config_channel_size(struct davinci_audio_dev *dev,
512 int channel_size) 512 int channel_size)
513{ 513{
514 u32 fmt = 0; 514 u32 fmt = 0;
515 u32 mask, rotate;
515 516
516 switch (channel_size) { 517 switch (channel_size) {
517 case DAVINCI_AUDIO_WORD_8: 518 case DAVINCI_AUDIO_WORD_8:
518 fmt = 0x03; 519 fmt = 0x03;
520 rotate = 6;
521 mask = 0x000000ff;
519 break; 522 break;
520 523
521 case DAVINCI_AUDIO_WORD_12: 524 case DAVINCI_AUDIO_WORD_12:
522 fmt = 0x05; 525 fmt = 0x05;
526 rotate = 5;
527 mask = 0x00000fff;
523 break; 528 break;
524 529
525 case DAVINCI_AUDIO_WORD_16: 530 case DAVINCI_AUDIO_WORD_16:
526 fmt = 0x07; 531 fmt = 0x07;
532 rotate = 4;
533 mask = 0x0000ffff;
527 break; 534 break;
528 535
529 case DAVINCI_AUDIO_WORD_20: 536 case DAVINCI_AUDIO_WORD_20:
530 fmt = 0x09; 537 fmt = 0x09;
538 rotate = 3;
539 mask = 0x000fffff;
531 break; 540 break;
532 541
533 case DAVINCI_AUDIO_WORD_24: 542 case DAVINCI_AUDIO_WORD_24:
534 fmt = 0x0B; 543 fmt = 0x0B;
544 rotate = 2;
545 mask = 0x00ffffff;
535 break; 546 break;
536 547
537 case DAVINCI_AUDIO_WORD_28: 548 case DAVINCI_AUDIO_WORD_28:
538 fmt = 0x0D; 549 fmt = 0x0D;
550 rotate = 1;
551 mask = 0x0fffffff;
539 break; 552 break;
540 553
541 case DAVINCI_AUDIO_WORD_32: 554 case DAVINCI_AUDIO_WORD_32:
542 fmt = 0x0F; 555 fmt = 0x0F;
556 rotate = 0;
557 mask = 0xffffffff;
543 break; 558 break;
544 559
545 default: 560 default:
@@ -550,6 +565,13 @@ static int davinci_config_channel_size(struct davinci_audio_dev *dev,
550 RXSSZ(fmt), RXSSZ(0x0F)); 565 RXSSZ(fmt), RXSSZ(0x0F));
551 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, 566 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
552 TXSSZ(fmt), TXSSZ(0x0F)); 567 TXSSZ(fmt), TXSSZ(0x0F));
568 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
569 TXROT(7));
570 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
571 RXROT(7));
572 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
573 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
574
553 return 0; 575 return 0;
554} 576}
555 577
@@ -638,7 +660,6 @@ static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
638 printk(KERN_ERR "playback tdm slot %d not supported\n", 660 printk(KERN_ERR "playback tdm slot %d not supported\n",
639 dev->tdm_slots); 661 dev->tdm_slots);
640 662
641 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0xFFFFFFFF);
642 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 663 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
643 } else { 664 } else {
644 /* bit stream is MSB first with no delay */ 665 /* bit stream is MSB first with no delay */
@@ -655,7 +676,6 @@ static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
655 printk(KERN_ERR "capture tdm slot %d not supported\n", 676 printk(KERN_ERR "capture tdm slot %d not supported\n",
656 dev->tdm_slots); 677 dev->tdm_slots);
657 678
658 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, 0xFFFFFFFF);
659 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 679 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
660 } 680 }
661} 681}