diff options
author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2009-08-15 06:20:44 -0400 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2009-08-15 06:20:44 -0400 |
commit | 08229de4b42816079ed5d15f0689fcd0af946d5e (patch) | |
tree | 7126dc7b220fbbce745cb5d9a8864e9690587da4 /sound/soc/davinci/davinci-i2s.c | |
parent | fbb474dedab871c7382858c374acd287dad4ab38 (diff) | |
parent | 2a708137fd7d3e0928f27157aaed8aba404b11c9 (diff) |
Merge branch 'for-2.6.32' into mxc
Conflicts:
sound/soc/Makefile
Diffstat (limited to 'sound/soc/davinci/davinci-i2s.c')
-rw-r--r-- | sound/soc/davinci/davinci-i2s.c | 340 |
1 files changed, 197 insertions, 143 deletions
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c index b1ea52fc83c7..12a6c549ee6e 100644 --- a/sound/soc/davinci/davinci-i2s.c +++ b/sound/soc/davinci/davinci-i2s.c | |||
@@ -22,6 +22,8 @@ | |||
22 | #include <sound/initval.h> | 22 | #include <sound/initval.h> |
23 | #include <sound/soc.h> | 23 | #include <sound/soc.h> |
24 | 24 | ||
25 | #include <mach/asp.h> | ||
26 | |||
25 | #include "davinci-pcm.h" | 27 | #include "davinci-pcm.h" |
26 | 28 | ||
27 | 29 | ||
@@ -63,6 +65,7 @@ | |||
63 | #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5) | 65 | #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5) |
64 | #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8) | 66 | #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8) |
65 | #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) | 67 | #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) |
68 | #define DAVINCI_MCBSP_RCR_RFIG (1 << 18) | ||
66 | #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) | 69 | #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) |
67 | 70 | ||
68 | #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) | 71 | #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) |
@@ -85,14 +88,6 @@ | |||
85 | #define DAVINCI_MCBSP_PCR_FSRM (1 << 10) | 88 | #define DAVINCI_MCBSP_PCR_FSRM (1 << 10) |
86 | #define DAVINCI_MCBSP_PCR_FSXM (1 << 11) | 89 | #define DAVINCI_MCBSP_PCR_FSXM (1 << 11) |
87 | 90 | ||
88 | #define MOD_REG_BIT(val, mask, set) do { \ | ||
89 | if (set) { \ | ||
90 | val |= mask; \ | ||
91 | } else { \ | ||
92 | val &= ~mask; \ | ||
93 | } \ | ||
94 | } while (0) | ||
95 | |||
96 | enum { | 91 | enum { |
97 | DAVINCI_MCBSP_WORD_8 = 0, | 92 | DAVINCI_MCBSP_WORD_8 = 0, |
98 | DAVINCI_MCBSP_WORD_12, | 93 | DAVINCI_MCBSP_WORD_12, |
@@ -112,6 +107,10 @@ static struct davinci_pcm_dma_params davinci_i2s_pcm_in = { | |||
112 | 107 | ||
113 | struct davinci_mcbsp_dev { | 108 | struct davinci_mcbsp_dev { |
114 | void __iomem *base; | 109 | void __iomem *base; |
110 | #define MOD_DSP_A 0 | ||
111 | #define MOD_DSP_B 1 | ||
112 | int mode; | ||
113 | u32 pcr; | ||
115 | struct clk *clk; | 114 | struct clk *clk; |
116 | struct davinci_pcm_dma_params *dma_params[2]; | 115 | struct davinci_pcm_dma_params *dma_params[2]; |
117 | }; | 116 | }; |
@@ -127,96 +126,100 @@ static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg) | |||
127 | return __raw_readl(dev->base + reg); | 126 | return __raw_readl(dev->base + reg); |
128 | } | 127 | } |
129 | 128 | ||
130 | static void davinci_mcbsp_start(struct snd_pcm_substream *substream) | 129 | static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback) |
130 | { | ||
131 | u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP; | ||
132 | /* The clock needs to toggle to complete reset. | ||
133 | * So, fake it by toggling the clk polarity. | ||
134 | */ | ||
135 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m); | ||
136 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr); | ||
137 | } | ||
138 | |||
139 | static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev, | ||
140 | struct snd_pcm_substream *substream) | ||
131 | { | 141 | { |
132 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | 142 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
133 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | ||
134 | struct snd_soc_device *socdev = rtd->socdev; | 143 | struct snd_soc_device *socdev = rtd->socdev; |
135 | struct snd_soc_platform *platform = socdev->card->platform; | 144 | struct snd_soc_platform *platform = socdev->card->platform; |
136 | u32 w; | 145 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
137 | int ret; | 146 | u32 spcr; |
138 | 147 | u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST; | |
139 | /* Start the sample generator and enable transmitter/receiver */ | 148 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
140 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | 149 | if (spcr & mask) { |
141 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1); | 150 | /* start off disabled */ |
142 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | 151 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, |
152 | spcr & ~mask); | ||
153 | toggle_clock(dev, playback); | ||
154 | } | ||
155 | if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM | | ||
156 | DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) { | ||
157 | /* Start the sample generator */ | ||
158 | spcr |= DAVINCI_MCBSP_SPCR_GRST; | ||
159 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | ||
160 | } | ||
143 | 161 | ||
144 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | 162 | if (playback) { |
145 | /* Stop the DMA to avoid data loss */ | 163 | /* Stop the DMA to avoid data loss */ |
146 | /* while the transmitter is out of reset to handle XSYNCERR */ | 164 | /* while the transmitter is out of reset to handle XSYNCERR */ |
147 | if (platform->pcm_ops->trigger) { | 165 | if (platform->pcm_ops->trigger) { |
148 | ret = platform->pcm_ops->trigger(substream, | 166 | int ret = platform->pcm_ops->trigger(substream, |
149 | SNDRV_PCM_TRIGGER_STOP); | 167 | SNDRV_PCM_TRIGGER_STOP); |
150 | if (ret < 0) | 168 | if (ret < 0) |
151 | printk(KERN_DEBUG "Playback DMA stop failed\n"); | 169 | printk(KERN_DEBUG "Playback DMA stop failed\n"); |
152 | } | 170 | } |
153 | 171 | ||
154 | /* Enable the transmitter */ | 172 | /* Enable the transmitter */ |
155 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | 173 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
156 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1); | 174 | spcr |= DAVINCI_MCBSP_SPCR_XRST; |
157 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | 175 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
158 | 176 | ||
159 | /* wait for any unexpected frame sync error to occur */ | 177 | /* wait for any unexpected frame sync error to occur */ |
160 | udelay(100); | 178 | udelay(100); |
161 | 179 | ||
162 | /* Disable the transmitter to clear any outstanding XSYNCERR */ | 180 | /* Disable the transmitter to clear any outstanding XSYNCERR */ |
163 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | 181 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
164 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0); | 182 | spcr &= ~DAVINCI_MCBSP_SPCR_XRST; |
165 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | 183 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
184 | toggle_clock(dev, playback); | ||
166 | 185 | ||
167 | /* Restart the DMA */ | 186 | /* Restart the DMA */ |
168 | if (platform->pcm_ops->trigger) { | 187 | if (platform->pcm_ops->trigger) { |
169 | ret = platform->pcm_ops->trigger(substream, | 188 | int ret = platform->pcm_ops->trigger(substream, |
170 | SNDRV_PCM_TRIGGER_START); | 189 | SNDRV_PCM_TRIGGER_START); |
171 | if (ret < 0) | 190 | if (ret < 0) |
172 | printk(KERN_DEBUG "Playback DMA start failed\n"); | 191 | printk(KERN_DEBUG "Playback DMA start failed\n"); |
173 | } | 192 | } |
174 | /* Enable the transmitter */ | ||
175 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | ||
176 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1); | ||
177 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | ||
178 | |||
179 | } else { | ||
180 | |||
181 | /* Enable the reciever */ | ||
182 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | ||
183 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1); | ||
184 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | ||
185 | } | 193 | } |
186 | 194 | ||
195 | /* Enable transmitter or receiver */ | ||
196 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | ||
197 | spcr |= mask; | ||
187 | 198 | ||
188 | /* Start frame sync */ | 199 | if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) { |
189 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | 200 | /* Start frame sync */ |
190 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1); | 201 | spcr |= DAVINCI_MCBSP_SPCR_FRST; |
191 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | 202 | } |
203 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | ||
192 | } | 204 | } |
193 | 205 | ||
194 | static void davinci_mcbsp_stop(struct snd_pcm_substream *substream) | 206 | static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback) |
195 | { | 207 | { |
196 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | 208 | u32 spcr; |
197 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | ||
198 | u32 w; | ||
199 | 209 | ||
200 | /* Reset transmitter/receiver and sample rate/frame sync generators */ | 210 | /* Reset transmitter/receiver and sample rate/frame sync generators */ |
201 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | 211 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
202 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST | | 212 | spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST); |
203 | DAVINCI_MCBSP_SPCR_FRST, 0); | 213 | spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST; |
204 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | 214 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
205 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0); | 215 | toggle_clock(dev, playback); |
206 | else | ||
207 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0); | ||
208 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | ||
209 | } | 216 | } |
210 | 217 | ||
211 | static int davinci_i2s_startup(struct snd_pcm_substream *substream, | 218 | static int davinci_i2s_startup(struct snd_pcm_substream *substream, |
212 | struct snd_soc_dai *dai) | 219 | struct snd_soc_dai *cpu_dai) |
213 | { | 220 | { |
214 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | 221 | struct davinci_mcbsp_dev *dev = cpu_dai->private_data; |
215 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | ||
216 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | ||
217 | |||
218 | cpu_dai->dma_data = dev->dma_params[substream->stream]; | 222 | cpu_dai->dma_data = dev->dma_params[substream->stream]; |
219 | |||
220 | return 0; | 223 | return 0; |
221 | } | 224 | } |
222 | 225 | ||
@@ -228,12 +231,11 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
228 | struct davinci_mcbsp_dev *dev = cpu_dai->private_data; | 231 | struct davinci_mcbsp_dev *dev = cpu_dai->private_data; |
229 | unsigned int pcr; | 232 | unsigned int pcr; |
230 | unsigned int srgr; | 233 | unsigned int srgr; |
231 | unsigned int rcr; | ||
232 | unsigned int xcr; | ||
233 | srgr = DAVINCI_MCBSP_SRGR_FSGM | | 234 | srgr = DAVINCI_MCBSP_SRGR_FSGM | |
234 | DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) | | 235 | DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) | |
235 | DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1); | 236 | DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1); |
236 | 237 | ||
238 | /* set master/slave audio interface */ | ||
237 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | 239 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
238 | case SND_SOC_DAIFMT_CBS_CFS: | 240 | case SND_SOC_DAIFMT_CBS_CFS: |
239 | /* cpu is master */ | 241 | /* cpu is master */ |
@@ -258,11 +260,8 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
258 | return -EINVAL; | 260 | return -EINVAL; |
259 | } | 261 | } |
260 | 262 | ||
261 | rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1); | 263 | /* interface format */ |
262 | xcr = DAVINCI_MCBSP_XCR_XFIG | DAVINCI_MCBSP_XCR_XFRLEN1(1); | ||
263 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | 264 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
264 | case SND_SOC_DAIFMT_DSP_B: | ||
265 | break; | ||
266 | case SND_SOC_DAIFMT_I2S: | 265 | case SND_SOC_DAIFMT_I2S: |
267 | /* Davinci doesn't support TRUE I2S, but some codecs will have | 266 | /* Davinci doesn't support TRUE I2S, but some codecs will have |
268 | * the left and right channels contiguous. This allows | 267 | * the left and right channels contiguous. This allows |
@@ -282,8 +281,10 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
282 | */ | 281 | */ |
283 | fmt ^= SND_SOC_DAIFMT_NB_IF; | 282 | fmt ^= SND_SOC_DAIFMT_NB_IF; |
284 | case SND_SOC_DAIFMT_DSP_A: | 283 | case SND_SOC_DAIFMT_DSP_A: |
285 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1); | 284 | dev->mode = MOD_DSP_A; |
286 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1); | 285 | break; |
286 | case SND_SOC_DAIFMT_DSP_B: | ||
287 | dev->mode = MOD_DSP_B; | ||
287 | break; | 288 | break; |
288 | default: | 289 | default: |
289 | printk(KERN_ERR "%s:bad format\n", __func__); | 290 | printk(KERN_ERR "%s:bad format\n", __func__); |
@@ -343,9 +344,8 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
343 | return -EINVAL; | 344 | return -EINVAL; |
344 | } | 345 | } |
345 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); | 346 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); |
347 | dev->pcr = pcr; | ||
346 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr); | 348 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr); |
347 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); | ||
348 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); | ||
349 | return 0; | 349 | return 0; |
350 | } | 350 | } |
351 | 351 | ||
@@ -353,31 +353,40 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, | |||
353 | struct snd_pcm_hw_params *params, | 353 | struct snd_pcm_hw_params *params, |
354 | struct snd_soc_dai *dai) | 354 | struct snd_soc_dai *dai) |
355 | { | 355 | { |
356 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | 356 | struct davinci_pcm_dma_params *dma_params = dai->dma_data; |
357 | struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data; | 357 | struct davinci_mcbsp_dev *dev = dai->private_data; |
358 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | ||
359 | struct snd_interval *i = NULL; | 358 | struct snd_interval *i = NULL; |
360 | int mcbsp_word_length; | 359 | int mcbsp_word_length; |
361 | u32 w; | 360 | unsigned int rcr, xcr, srgr; |
361 | u32 spcr; | ||
362 | 362 | ||
363 | /* general line settings */ | 363 | /* general line settings */ |
364 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | 364 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
365 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { | 365 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
366 | w |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE; | 366 | spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
367 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | 367 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
368 | } else { | 368 | } else { |
369 | w |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE; | 369 | spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
370 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | 370 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
371 | } | 371 | } |
372 | 372 | ||
373 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); | 373 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); |
374 | w = DAVINCI_MCBSP_SRGR_FSGM; | 374 | srgr = DAVINCI_MCBSP_SRGR_FSGM; |
375 | MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1); | 375 | srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); |
376 | 376 | ||
377 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); | 377 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); |
378 | MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1); | 378 | srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); |
379 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w); | 379 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); |
380 | 380 | ||
381 | rcr = DAVINCI_MCBSP_RCR_RFIG; | ||
382 | xcr = DAVINCI_MCBSP_XCR_XFIG; | ||
383 | if (dev->mode == MOD_DSP_B) { | ||
384 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0); | ||
385 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0); | ||
386 | } else { | ||
387 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1); | ||
388 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1); | ||
389 | } | ||
381 | /* Determine xfer data type */ | 390 | /* Determine xfer data type */ |
382 | switch (params_format(params)) { | 391 | switch (params_format(params)) { |
383 | case SNDRV_PCM_FORMAT_S8: | 392 | case SNDRV_PCM_FORMAT_S8: |
@@ -397,18 +406,31 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, | |||
397 | return -EINVAL; | 406 | return -EINVAL; |
398 | } | 407 | } |
399 | 408 | ||
400 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { | 409 | dma_params->acnt = dma_params->data_type; |
401 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG); | 410 | rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(1); |
402 | MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | | 411 | xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(1); |
403 | DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1); | ||
404 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w); | ||
405 | 412 | ||
406 | } else { | 413 | rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | |
407 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG); | 414 | DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length); |
408 | MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) | | 415 | xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) | |
409 | DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1); | 416 | DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length); |
410 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w); | ||
411 | 417 | ||
418 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | ||
419 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); | ||
420 | else | ||
421 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); | ||
422 | return 0; | ||
423 | } | ||
424 | |||
425 | static int davinci_i2s_prepare(struct snd_pcm_substream *substream, | ||
426 | struct snd_soc_dai *dai) | ||
427 | { | ||
428 | struct davinci_mcbsp_dev *dev = dai->private_data; | ||
429 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | ||
430 | davinci_mcbsp_stop(dev, playback); | ||
431 | if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) { | ||
432 | /* codec is master */ | ||
433 | davinci_mcbsp_start(dev, substream); | ||
412 | } | 434 | } |
413 | return 0; | 435 | return 0; |
414 | } | 436 | } |
@@ -416,35 +438,72 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, | |||
416 | static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd, | 438 | static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
417 | struct snd_soc_dai *dai) | 439 | struct snd_soc_dai *dai) |
418 | { | 440 | { |
441 | struct davinci_mcbsp_dev *dev = dai->private_data; | ||
419 | int ret = 0; | 442 | int ret = 0; |
443 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | ||
444 | if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) | ||
445 | return 0; /* return if codec is master */ | ||
420 | 446 | ||
421 | switch (cmd) { | 447 | switch (cmd) { |
422 | case SNDRV_PCM_TRIGGER_START: | 448 | case SNDRV_PCM_TRIGGER_START: |
423 | case SNDRV_PCM_TRIGGER_RESUME: | 449 | case SNDRV_PCM_TRIGGER_RESUME: |
424 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | 450 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
425 | davinci_mcbsp_start(substream); | 451 | davinci_mcbsp_start(dev, substream); |
426 | break; | 452 | break; |
427 | case SNDRV_PCM_TRIGGER_STOP: | 453 | case SNDRV_PCM_TRIGGER_STOP: |
428 | case SNDRV_PCM_TRIGGER_SUSPEND: | 454 | case SNDRV_PCM_TRIGGER_SUSPEND: |
429 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | 455 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
430 | davinci_mcbsp_stop(substream); | 456 | davinci_mcbsp_stop(dev, playback); |
431 | break; | 457 | break; |
432 | default: | 458 | default: |
433 | ret = -EINVAL; | 459 | ret = -EINVAL; |
434 | } | 460 | } |
435 | |||
436 | return ret; | 461 | return ret; |
437 | } | 462 | } |
438 | 463 | ||
439 | static int davinci_i2s_probe(struct platform_device *pdev, | 464 | static void davinci_i2s_shutdown(struct snd_pcm_substream *substream, |
440 | struct snd_soc_dai *dai) | 465 | struct snd_soc_dai *dai) |
466 | { | ||
467 | struct davinci_mcbsp_dev *dev = dai->private_data; | ||
468 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | ||
469 | davinci_mcbsp_stop(dev, playback); | ||
470 | } | ||
471 | |||
472 | #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000 | ||
473 | |||
474 | static struct snd_soc_dai_ops davinci_i2s_dai_ops = { | ||
475 | .startup = davinci_i2s_startup, | ||
476 | .shutdown = davinci_i2s_shutdown, | ||
477 | .prepare = davinci_i2s_prepare, | ||
478 | .trigger = davinci_i2s_trigger, | ||
479 | .hw_params = davinci_i2s_hw_params, | ||
480 | .set_fmt = davinci_i2s_set_dai_fmt, | ||
481 | |||
482 | }; | ||
483 | |||
484 | struct snd_soc_dai davinci_i2s_dai = { | ||
485 | .name = "davinci-i2s", | ||
486 | .id = 0, | ||
487 | .playback = { | ||
488 | .channels_min = 2, | ||
489 | .channels_max = 2, | ||
490 | .rates = DAVINCI_I2S_RATES, | ||
491 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | ||
492 | .capture = { | ||
493 | .channels_min = 2, | ||
494 | .channels_max = 2, | ||
495 | .rates = DAVINCI_I2S_RATES, | ||
496 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | ||
497 | .ops = &davinci_i2s_dai_ops, | ||
498 | |||
499 | }; | ||
500 | EXPORT_SYMBOL_GPL(davinci_i2s_dai); | ||
501 | |||
502 | static int davinci_i2s_probe(struct platform_device *pdev) | ||
441 | { | 503 | { |
442 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | 504 | struct snd_platform_data *pdata = pdev->dev.platform_data; |
443 | struct snd_soc_card *card = socdev->card; | ||
444 | struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai; | ||
445 | struct davinci_mcbsp_dev *dev; | 505 | struct davinci_mcbsp_dev *dev; |
446 | struct resource *mem, *ioarea; | 506 | struct resource *mem, *ioarea, *res; |
447 | struct evm_snd_platform_data *pdata; | ||
448 | int ret; | 507 | int ret; |
449 | 508 | ||
450 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 509 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
@@ -466,8 +525,6 @@ static int davinci_i2s_probe(struct platform_device *pdev, | |||
466 | goto err_release_region; | 525 | goto err_release_region; |
467 | } | 526 | } |
468 | 527 | ||
469 | cpu_dai->private_data = dev; | ||
470 | |||
471 | dev->clk = clk_get(&pdev->dev, NULL); | 528 | dev->clk = clk_get(&pdev->dev, NULL); |
472 | if (IS_ERR(dev->clk)) { | 529 | if (IS_ERR(dev->clk)) { |
473 | ret = -ENODEV; | 530 | ret = -ENODEV; |
@@ -476,18 +533,37 @@ static int davinci_i2s_probe(struct platform_device *pdev, | |||
476 | clk_enable(dev->clk); | 533 | clk_enable(dev->clk); |
477 | 534 | ||
478 | dev->base = (void __iomem *)IO_ADDRESS(mem->start); | 535 | dev->base = (void __iomem *)IO_ADDRESS(mem->start); |
479 | pdata = pdev->dev.platform_data; | ||
480 | 536 | ||
481 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out; | 537 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out; |
482 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch; | ||
483 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr = | 538 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr = |
484 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG); | 539 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG); |
485 | 540 | ||
486 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in; | 541 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in; |
487 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch; | ||
488 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr = | 542 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr = |
489 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG); | 543 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG); |
490 | 544 | ||
545 | /* first TX, then RX */ | ||
546 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | ||
547 | if (!res) { | ||
548 | dev_err(&pdev->dev, "no DMA resource\n"); | ||
549 | ret = -ENXIO; | ||
550 | goto err_free_mem; | ||
551 | } | ||
552 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = res->start; | ||
553 | |||
554 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | ||
555 | if (!res) { | ||
556 | dev_err(&pdev->dev, "no DMA resource\n"); | ||
557 | ret = -ENXIO; | ||
558 | goto err_free_mem; | ||
559 | } | ||
560 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = res->start; | ||
561 | |||
562 | davinci_i2s_dai.private_data = dev; | ||
563 | ret = snd_soc_register_dai(&davinci_i2s_dai); | ||
564 | if (ret != 0) | ||
565 | goto err_free_mem; | ||
566 | |||
491 | return 0; | 567 | return 0; |
492 | 568 | ||
493 | err_free_mem: | 569 | err_free_mem: |
@@ -498,62 +574,40 @@ err_release_region: | |||
498 | return ret; | 574 | return ret; |
499 | } | 575 | } |
500 | 576 | ||
501 | static void davinci_i2s_remove(struct platform_device *pdev, | 577 | static int davinci_i2s_remove(struct platform_device *pdev) |
502 | struct snd_soc_dai *dai) | ||
503 | { | 578 | { |
504 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | 579 | struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data; |
505 | struct snd_soc_card *card = socdev->card; | ||
506 | struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai; | ||
507 | struct davinci_mcbsp_dev *dev = cpu_dai->private_data; | ||
508 | struct resource *mem; | 580 | struct resource *mem; |
509 | 581 | ||
582 | snd_soc_unregister_dai(&davinci_i2s_dai); | ||
510 | clk_disable(dev->clk); | 583 | clk_disable(dev->clk); |
511 | clk_put(dev->clk); | 584 | clk_put(dev->clk); |
512 | dev->clk = NULL; | 585 | dev->clk = NULL; |
513 | |||
514 | kfree(dev); | 586 | kfree(dev); |
515 | |||
516 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 587 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
517 | release_mem_region(mem->start, (mem->end - mem->start) + 1); | 588 | release_mem_region(mem->start, (mem->end - mem->start) + 1); |
518 | } | ||
519 | 589 | ||
520 | #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000 | 590 | return 0; |
521 | 591 | } | |
522 | static struct snd_soc_dai_ops davinci_i2s_dai_ops = { | ||
523 | .startup = davinci_i2s_startup, | ||
524 | .trigger = davinci_i2s_trigger, | ||
525 | .hw_params = davinci_i2s_hw_params, | ||
526 | .set_fmt = davinci_i2s_set_dai_fmt, | ||
527 | }; | ||
528 | 592 | ||
529 | struct snd_soc_dai davinci_i2s_dai = { | 593 | static struct platform_driver davinci_mcbsp_driver = { |
530 | .name = "davinci-i2s", | 594 | .probe = davinci_i2s_probe, |
531 | .id = 0, | 595 | .remove = davinci_i2s_remove, |
532 | .probe = davinci_i2s_probe, | 596 | .driver = { |
533 | .remove = davinci_i2s_remove, | 597 | .name = "davinci-asp", |
534 | .playback = { | 598 | .owner = THIS_MODULE, |
535 | .channels_min = 2, | 599 | }, |
536 | .channels_max = 2, | ||
537 | .rates = DAVINCI_I2S_RATES, | ||
538 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | ||
539 | .capture = { | ||
540 | .channels_min = 2, | ||
541 | .channels_max = 2, | ||
542 | .rates = DAVINCI_I2S_RATES, | ||
543 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | ||
544 | .ops = &davinci_i2s_dai_ops, | ||
545 | }; | 600 | }; |
546 | EXPORT_SYMBOL_GPL(davinci_i2s_dai); | ||
547 | 601 | ||
548 | static int __init davinci_i2s_init(void) | 602 | static int __init davinci_i2s_init(void) |
549 | { | 603 | { |
550 | return snd_soc_register_dai(&davinci_i2s_dai); | 604 | return platform_driver_register(&davinci_mcbsp_driver); |
551 | } | 605 | } |
552 | module_init(davinci_i2s_init); | 606 | module_init(davinci_i2s_init); |
553 | 607 | ||
554 | static void __exit davinci_i2s_exit(void) | 608 | static void __exit davinci_i2s_exit(void) |
555 | { | 609 | { |
556 | snd_soc_unregister_dai(&davinci_i2s_dai); | 610 | platform_driver_unregister(&davinci_mcbsp_driver); |
557 | } | 611 | } |
558 | module_exit(davinci_i2s_exit); | 612 | module_exit(davinci_i2s_exit); |
559 | 613 | ||