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authorMark Brown <broonie@opensource.wolfsonmicro.com>2010-03-15 13:46:02 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-03-16 11:56:34 -0400
commit73b34ead7429789f35eea147a3e185abd61c7d94 (patch)
treebc70d0508b5ca6caf276d42e733e79d6838c6e1a /sound/soc/codecs/wm8903.h
parentda34183e640ed380f708bf9ebcd592afda619028 (diff)
ASoC: Add GPIO configuration support for WM8903
Allow users to pass in a default configuration for the GPIOs of the WM8903 as platform data. This allows configuration of the pin muxing of the device. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Diffstat (limited to 'sound/soc/codecs/wm8903.h')
-rw-r--r--sound/soc/codecs/wm8903.h195
1 files changed, 0 insertions, 195 deletions
diff --git a/sound/soc/codecs/wm8903.h b/sound/soc/codecs/wm8903.h
index 0ea27e2b9963..551736cf2195 100644
--- a/sound/soc/codecs/wm8903.h
+++ b/sound/soc/codecs/wm8903.h
@@ -1135,201 +1135,6 @@ extern struct snd_soc_codec_device soc_codec_dev_wm8903;
1135#define WM8903_MASK_WRITE_ENA_WIDTH 1 /* MASK_WRITE_ENA */ 1135#define WM8903_MASK_WRITE_ENA_WIDTH 1 /* MASK_WRITE_ENA */
1136 1136
1137/* 1137/*
1138 * R116 (0x74) - GPIO Control 1
1139 */
1140#define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */
1141#define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */
1142#define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */
1143#define WM8903_GP1_DIR 0x0080 /* GP1_DIR */
1144#define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */
1145#define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */
1146#define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */
1147#define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */
1148#define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */
1149#define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */
1150#define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
1151#define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */
1152#define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */
1153#define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */
1154#define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */
1155#define WM8903_GP1_LVL 0x0010 /* GP1_LVL */
1156#define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */
1157#define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */
1158#define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */
1159#define WM8903_GP1_PD 0x0008 /* GP1_PD */
1160#define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */
1161#define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */
1162#define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */
1163#define WM8903_GP1_PU 0x0004 /* GP1_PU */
1164#define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */
1165#define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */
1166#define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */
1167#define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */
1168#define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */
1169#define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */
1170#define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */
1171#define WM8903_GP1_DB 0x0001 /* GP1_DB */
1172#define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */
1173#define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */
1174#define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */
1175
1176/*
1177 * R117 (0x75) - GPIO Control 2
1178 */
1179#define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */
1180#define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */
1181#define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */
1182#define WM8903_GP2_DIR 0x0080 /* GP2_DIR */
1183#define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */
1184#define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */
1185#define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */
1186#define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */
1187#define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */
1188#define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */
1189#define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
1190#define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */
1191#define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */
1192#define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */
1193#define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */
1194#define WM8903_GP2_LVL 0x0010 /* GP2_LVL */
1195#define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */
1196#define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */
1197#define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */
1198#define WM8903_GP2_PD 0x0008 /* GP2_PD */
1199#define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */
1200#define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */
1201#define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */
1202#define WM8903_GP2_PU 0x0004 /* GP2_PU */
1203#define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */
1204#define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */
1205#define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */
1206#define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */
1207#define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */
1208#define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */
1209#define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */
1210#define WM8903_GP2_DB 0x0001 /* GP2_DB */
1211#define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */
1212#define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */
1213#define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */
1214
1215/*
1216 * R118 (0x76) - GPIO Control 3
1217 */
1218#define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */
1219#define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */
1220#define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */
1221#define WM8903_GP3_DIR 0x0080 /* GP3_DIR */
1222#define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */
1223#define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */
1224#define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */
1225#define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */
1226#define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */
1227#define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */
1228#define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
1229#define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */
1230#define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */
1231#define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */
1232#define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */
1233#define WM8903_GP3_LVL 0x0010 /* GP3_LVL */
1234#define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */
1235#define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */
1236#define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */
1237#define WM8903_GP3_PD 0x0008 /* GP3_PD */
1238#define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */
1239#define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */
1240#define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */
1241#define WM8903_GP3_PU 0x0004 /* GP3_PU */
1242#define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */
1243#define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */
1244#define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */
1245#define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */
1246#define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */
1247#define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */
1248#define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */
1249#define WM8903_GP3_DB 0x0001 /* GP3_DB */
1250#define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */
1251#define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */
1252#define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */
1253
1254/*
1255 * R119 (0x77) - GPIO Control 4
1256 */
1257#define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */
1258#define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */
1259#define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */
1260#define WM8903_GP4_DIR 0x0080 /* GP4_DIR */
1261#define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */
1262#define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */
1263#define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */
1264#define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */
1265#define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */
1266#define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */
1267#define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
1268#define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */
1269#define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */
1270#define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */
1271#define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */
1272#define WM8903_GP4_LVL 0x0010 /* GP4_LVL */
1273#define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */
1274#define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */
1275#define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */
1276#define WM8903_GP4_PD 0x0008 /* GP4_PD */
1277#define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */
1278#define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */
1279#define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */
1280#define WM8903_GP4_PU 0x0004 /* GP4_PU */
1281#define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */
1282#define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */
1283#define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */
1284#define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */
1285#define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */
1286#define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */
1287#define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */
1288#define WM8903_GP4_DB 0x0001 /* GP4_DB */
1289#define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */
1290#define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */
1291#define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */
1292
1293/*
1294 * R120 (0x78) - GPIO Control 5
1295 */
1296#define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */
1297#define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */
1298#define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */
1299#define WM8903_GP5_DIR 0x0080 /* GP5_DIR */
1300#define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */
1301#define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */
1302#define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */
1303#define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */
1304#define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */
1305#define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */
1306#define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
1307#define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */
1308#define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */
1309#define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */
1310#define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */
1311#define WM8903_GP5_LVL 0x0010 /* GP5_LVL */
1312#define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */
1313#define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */
1314#define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */
1315#define WM8903_GP5_PD 0x0008 /* GP5_PD */
1316#define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */
1317#define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */
1318#define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */
1319#define WM8903_GP5_PU 0x0004 /* GP5_PU */
1320#define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */
1321#define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */
1322#define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */
1323#define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */
1324#define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */
1325#define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */
1326#define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */
1327#define WM8903_GP5_DB 0x0001 /* GP5_DB */
1328#define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */
1329#define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */
1330#define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */
1331
1332/*
1333 * R121 (0x79) - Interrupt Status 1 1138 * R121 (0x79) - Interrupt Status 1
1334 */ 1139 */
1335#define WM8903_MICSHRT_EINT 0x8000 /* MICSHRT_EINT */ 1140#define WM8903_MICSHRT_EINT 0x8000 /* MICSHRT_EINT */