Merge branch 'next/devel2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc

* 'next/devel2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (47 commits)
  OMAP: Add debugfs node to show the summary of all clocks
  OMAP2+: hwmod: Follow the recommended PRCM module enable sequence
  OMAP2+: clock: allow per-SoC clock init code to prevent clockdomain calls from clock code
  OMAP2+: clockdomain: Add per clkdm lock to prevent concurrent state programming
  OMAP2+: PM: idle clkdms only if already in idle
  OMAP2+: clockdomain: add clkdm_in_hwsup()
  OMAP2+: clockdomain: Add 2 APIs to control clockdomain from hwmod framework
  OMAP: clockdomain: Remove redundant call to pwrdm_wait_transition()
  OMAP4: hwmod: Introduce the module control in hwmod control
  OMAP4: cm: Add two new APIs for modulemode control
  OMAP4: hwmod data: Add modulemode entry in omap_hwmod structure
  OMAP4: hwmod data: Add PRM context register offset
  OMAP4: prm: Remove deprecated functions
  OMAP4: prm: Replace warm reset API with the offset based version
  OMAP4: hwmod: Replace RSTCTRL absolute address with offset macros
  OMAP: hwmod: Wait the idle status to be disabled
  OMAP4: hwmod: Replace CLKCTRL absolute address with offset macros
  OMAP2+: hwmod: Init clkdm field at boot time
  OMAP4: hwmod data: Add clock domain attribute
  OMAP4: clock data: Add missing divider selection for auxclks
  ...

1 files changed, 1 insertions, 118 deletions

diff --git a/sound/soc/codecs/twl6040.h b/sound/soc/codecs/twl6040.h
index 23aeed0963e6..d8de67869dd9 100644
--- a/sound/soc/codecs/twl6040.h
+++ b/sound/soc/codecs/twl6040.h
@@ -22,125 +22,8 @@
 #ifndef __TWL6040_H__
 #define __TWL6040_H__
 
-#define TWL6040_REG_ASICID              0x01
-#define TWL6040_REG_ASICREV             0x02
-#define TWL6040_REG_INTID               0x03
-#define TWL6040_REG_INTMR               0x04
-#define TWL6040_REG_NCPCTL              0x05
-#define TWL6040_REG_LDOCTL              0x06
-#define TWL6040_REG_HPPLLCTL            0x07
-#define TWL6040_REG_LPPLLCTL            0x08
-#define TWL6040_REG_LPPLLDIV            0x09
-#define TWL6040_REG_AMICBCTL            0x0A
-#define TWL6040_REG_DMICBCTL            0x0B
-#define TWL6040_REG_MICLCTL             0x0C
-#define TWL6040_REG_MICRCTL             0x0D
-#define TWL6040_REG_MICGAIN             0x0E
-#define TWL6040_REG_LINEGAIN            0x0F
-#define TWL6040_REG_HSLCTL              0x10
-#define TWL6040_REG_HSRCTL              0x11
-#define TWL6040_REG_HSGAIN              0x12
-#define TWL6040_REG_EARCTL              0x13
-#define TWL6040_REG_HFLCTL              0x14
-#define TWL6040_REG_HFLGAIN             0x15
-#define TWL6040_REG_HFRCTL              0x16
-#define TWL6040_REG_HFRGAIN             0x17
-#define TWL6040_REG_VIBCTLL             0x18
-#define TWL6040_REG_VIBDATL             0x19
-#define TWL6040_REG_VIBCTLR             0x1A
-#define TWL6040_REG_VIBDATR             0x1B
-#define TWL6040_REG_HKCTL1              0x1C
-#define TWL6040_REG_HKCTL2              0x1D
-#define TWL6040_REG_GPOCTL              0x1E
-#define TWL6040_REG_ALB                 0x1F
-#define TWL6040_REG_DLB                 0x20
-#define TWL6040_REG_TRIM1               0x28
-#define TWL6040_REG_TRIM2               0x29
-#define TWL6040_REG_TRIM3               0x2A
-#define TWL6040_REG_HSOTRIM             0x2B
-#define TWL6040_REG_HFOTRIM             0x2C
-#define TWL6040_REG_ACCCTL              0x2D
-#define TWL6040_REG_STATUS              0x2E
-
-#define TWL6040_CACHEREGNUM             (TWL6040_REG_STATUS + 1)
-
-#define TWL6040_VIOREGNUM               18
-#define TWL6040_VDDREGNUM               21
-
-/* INTID (0x03) fields */
-
-#define TWL6040_THINT                   0x01
-#define TWL6040_PLUGINT                 0x02
-#define TWL6040_UNPLUGINT               0x04
-#define TWL6040_HOOKINT                 0x08
-#define TWL6040_HFINT                   0x10
-#define TWL6040_VIBINT                  0x20
-#define TWL6040_READYINT                0x40
-
-/* INTMR (0x04) fields */
-
-#define TWL6040_PLUGMSK                 0x02
-#define TWL6040_READYMSK                0x40
-#define TWL6040_ALLINT_MSK              0x7B
-
-/* NCPCTL (0x05) fields */
-
-#define TWL6040_NCPENA                  0x01
-#define TWL6040_NCPOPEN                 0x40
-
-/* LDOCTL (0x06) fields */
-
-#define TWL6040_LSLDOENA                0x01
-#define TWL6040_HSLDOENA                0x04
-#define TWL6040_REFENA                  0x40
-#define TWL6040_OSCENA                  0x80
-
-/* HPPLLCTL (0x07) fields */
-
-#define TWL6040_HPLLENA                 0x01
-#define TWL6040_HPLLRST                 0x02
-#define TWL6040_HPLLBP                  0x04
-#define TWL6040_HPLLSQRENA              0x08
-#define TWL6040_HPLLSQRBP               0x10
-#define TWL6040_MCLK_12000KHZ           (0 << 5)
-#define TWL6040_MCLK_19200KHZ           (1 << 5)
-#define TWL6040_MCLK_26000KHZ           (2 << 5)
-#define TWL6040_MCLK_38400KHZ           (3 << 5)
-#define TWL6040_MCLK_MSK                0x60
-
-/* LPPLLCTL (0x08) fields */
-
-#define TWL6040_LPLLENA                 0x01
-#define TWL6040_LPLLRST                 0x02
-#define TWL6040_LPLLSEL                 0x04
-#define TWL6040_LPLLFIN                 0x08
-#define TWL6040_HPLLSEL                 0x10
-
-/* HSLCTL (0x10) fields */
-
-#define TWL6040_HSDACMODEL              0x02
-#define TWL6040_HSDRVMODEL              0x08
-
-/* HSRCTL (0x11) fields */
-
-#define TWL6040_HSDACMODER              0x02
-#define TWL6040_HSDRVMODER              0x08
-
-/* ACCCTL (0x2D) fields */
-
-#define TWL6040_RESETSPLIT              0x04
-
-#define TWL6040_SYSCLK_SEL_LPPLL        1
-#define TWL6040_SYSCLK_SEL_HPPLL        2
-
-#define TWL6040_HPPLL_ID                1
-#define TWL6040_LPPLL_ID                2
-
-/* STATUS (0x2E) fields */
-
-#define TWL6040_PLUGCOMP                0x02
-
 void twl6040_hs_jack_detect(struct snd_soc_codec *codec,
                             struct snd_soc_jack *jack, int report);
+int twl6040_get_clk_id(struct snd_soc_codec *codec);
 
 #endif /* End of __TWL6040_H__ */