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authorPavel Hofman <dustin@seznam.cz>2007-04-24 06:27:36 -0400
committerJaroslav Kysela <perex@suse.cz>2007-05-11 10:56:10 -0400
commitc5a30f85fd56c06efddbe6f4885c7968245c2d8a (patch)
tree813874ce9f72e9e2ae01f1deeb87246dc83f8f45 /sound/pci
parentbccad14e9a931027b72f20fe7caba68fea760e7b (diff)
[ALSA] ice1724 - Misc fixes for Prodigy192
- always set 256fs in SPDIF master clock mode - disable deemphasis filter in AK4114 for Prodigy192 Signed-off-by: Pavel Hofman <dustin@seznam.cz> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
Diffstat (limited to 'sound/pci')
-rw-r--r--sound/pci/ice1712/ice1724.c5
-rw-r--r--sound/pci/ice1712/prodigy192.c12
2 files changed, 16 insertions, 1 deletions
diff --git a/sound/pci/ice1712/ice1724.c b/sound/pci/ice1712/ice1724.c
index 6a29bcf19042..ee620dea7ef3 100644
--- a/sound/pci/ice1712/ice1724.c
+++ b/sound/pci/ice1712/ice1724.c
@@ -1666,7 +1666,12 @@ static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
1666 spin_lock_irq(&ice->reg_lock); 1666 spin_lock_irq(&ice->reg_lock);
1667 oval = inb(ICEMT1724(ice, RATE)); 1667 oval = inb(ICEMT1724(ice, RATE));
1668 if (ucontrol->value.enumerated.item[0] == spdif) { 1668 if (ucontrol->value.enumerated.item[0] == spdif) {
1669 unsigned char i2s_oval;
1669 outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE)); 1670 outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
1671 /* setting 256fs */
1672 i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
1673 outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X,
1674 ICEMT1724(ice, I2S_FORMAT));
1670 } else { 1675 } else {
1671 rate = rates[ucontrol->value.integer.value[0] % 15]; 1676 rate = rates[ucontrol->value.integer.value[0] % 15];
1672 if (rate <= get_max_rate(ice)) { 1677 if (rate <= get_max_rate(ice)) {
diff --git a/sound/pci/ice1712/prodigy192.c b/sound/pci/ice1712/prodigy192.c
index ae08a079a413..f03c02c07743 100644
--- a/sound/pci/ice1712/prodigy192.c
+++ b/sound/pci/ice1712/prodigy192.c
@@ -26,6 +26,13 @@
26 * CCLK (pin 34) -- GPIO9 pin 76 26 * CCLK (pin 34) -- GPIO9 pin 76
27 * CSN (pin 35) -- GPIO8 pin 75 27 * CSN (pin 35) -- GPIO8 pin 75
28 * - output data Mode 7 (24bit, I2S, slave) 28 * - output data Mode 7 (24bit, I2S, slave)
29 * - both MCKO1 and MCKO2 of ak4114 are fed to FPGA, which
30 * outputs master clock to SPMCLKIN of ice1724.
31 * Experimentally I found out that only a combination of
32 * OCKS0=1, OCKS1=1 (128fs, 64fs output) and ice1724 -
33 * VT1724_MT_I2S_MCLK_128X=0 (256fs input) yields correct
34 * sampling rate. That means the the FPGA doubles the
35 * MCK01 rate.
29 * 36 *
30 * Copyright (c) 2003 Takashi Iwai <tiwai@suse.de> 37 * Copyright (c) 2003 Takashi Iwai <tiwai@suse.de>
31 * Copyright (c) 2003 Dimitromanolakis Apostolos <apostol@cs.utoronto.ca> 38 * Copyright (c) 2003 Dimitromanolakis Apostolos <apostol@cs.utoronto.ca>
@@ -714,7 +721,10 @@ static int prodigy192_ak4114_init(struct snd_ice1712 *ice)
714{ 721{
715 static const unsigned char ak4114_init_vals[] = { 722 static const unsigned char ak4114_init_vals[] = {
716 AK4114_RST | AK4114_PWN | AK4114_OCKS0 | AK4114_OCKS1, 723 AK4114_RST | AK4114_PWN | AK4114_OCKS0 | AK4114_OCKS1,
717 AK4114_DIF_I24I2S, /* ice1724 expects I2S and provides clock */ 724 /* ice1724 expects I2S and provides clock,
725 * DEM0 disables the deemphasis filter
726 */
727 AK4114_DIF_I24I2S | AK4114_DEM0 ,
718 AK4114_TX1E, 728 AK4114_TX1E,
719 AK4114_EFH_1024 | AK4114_DIT, /* default input RX0 */ 729 AK4114_EFH_1024 | AK4114_DIT, /* default input RX0 */
720 0, 730 0,