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authorIngo Molnar <mingo@elte.hu>2009-04-20 12:08:07 -0400
committerIngo Molnar <mingo@elte.hu>2009-04-20 12:08:12 -0400
commit62d170290979e0bb805d969cca4ea852bdd45260 (patch)
tree837372297501a2d144358b44e7db3f88c5612aa2 /sound/pci/hda/hda_intel.c
parent8b5b94e4e9813cdd77103827f48d58c806ab45c6 (diff)
parentd91dfbb41bb2e9bdbfbd2cc7078ed7436eab027a (diff)
Merge branch 'linus' into x86/urgent
Merge reason: We need the x86/uv updates from upstream, to queue up dependent fix. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'sound/pci/hda/hda_intel.c')
-rw-r--r--sound/pci/hda/hda_intel.c47
1 files changed, 29 insertions, 18 deletions
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 30829ee920c3..21e99cfa8c49 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -312,6 +312,8 @@ struct azx_dev {
312 unsigned int period_bytes; /* size of the period in bytes */ 312 unsigned int period_bytes; /* size of the period in bytes */
313 unsigned int frags; /* number for period in the play buffer */ 313 unsigned int frags; /* number for period in the play buffer */
314 unsigned int fifo_size; /* FIFO size */ 314 unsigned int fifo_size; /* FIFO size */
315 unsigned long start_jiffies; /* start + minimum jiffies */
316 unsigned long min_jiffies; /* minimum jiffies before position is valid */
315 317
316 void __iomem *sd_addr; /* stream descriptor pointer */ 318 void __iomem *sd_addr; /* stream descriptor pointer */
317 319
@@ -330,7 +332,7 @@ struct azx_dev {
330 unsigned int opened :1; 332 unsigned int opened :1;
331 unsigned int running :1; 333 unsigned int running :1;
332 unsigned int irq_pending :1; 334 unsigned int irq_pending :1;
333 unsigned int irq_ignore :1; 335 unsigned int start_flag: 1; /* stream full start flag */
334 /* 336 /*
335 * For VIA: 337 * For VIA:
336 * A flag to ensure DMA position is 0 338 * A flag to ensure DMA position is 0
@@ -975,7 +977,7 @@ static irqreturn_t azx_interrupt(int irq, void *dev_id)
975 struct azx *chip = dev_id; 977 struct azx *chip = dev_id;
976 struct azx_dev *azx_dev; 978 struct azx_dev *azx_dev;
977 u32 status; 979 u32 status;
978 int i; 980 int i, ok;
979 981
980 spin_lock(&chip->reg_lock); 982 spin_lock(&chip->reg_lock);
981 983
@@ -991,18 +993,14 @@ static irqreturn_t azx_interrupt(int irq, void *dev_id)
991 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 993 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
992 if (!azx_dev->substream || !azx_dev->running) 994 if (!azx_dev->substream || !azx_dev->running)
993 continue; 995 continue;
994 /* ignore the first dummy IRQ (due to pos_adj) */
995 if (azx_dev->irq_ignore) {
996 azx_dev->irq_ignore = 0;
997 continue;
998 }
999 /* check whether this IRQ is really acceptable */ 996 /* check whether this IRQ is really acceptable */
1000 if (azx_position_ok(chip, azx_dev)) { 997 ok = azx_position_ok(chip, azx_dev);
998 if (ok == 1) {
1001 azx_dev->irq_pending = 0; 999 azx_dev->irq_pending = 0;
1002 spin_unlock(&chip->reg_lock); 1000 spin_unlock(&chip->reg_lock);
1003 snd_pcm_period_elapsed(azx_dev->substream); 1001 snd_pcm_period_elapsed(azx_dev->substream);
1004 spin_lock(&chip->reg_lock); 1002 spin_lock(&chip->reg_lock);
1005 } else if (chip->bus && chip->bus->workq) { 1003 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1006 /* bogus IRQ, process it later */ 1004 /* bogus IRQ, process it later */
1007 azx_dev->irq_pending = 1; 1005 azx_dev->irq_pending = 1;
1008 queue_work(chip->bus->workq, 1006 queue_work(chip->bus->workq,
@@ -1088,7 +1086,6 @@ static int azx_setup_periods(struct azx *chip,
1088 bdl = (u32 *)azx_dev->bdl.area; 1086 bdl = (u32 *)azx_dev->bdl.area;
1089 ofs = 0; 1087 ofs = 0;
1090 azx_dev->frags = 0; 1088 azx_dev->frags = 0;
1091 azx_dev->irq_ignore = 0;
1092 pos_adj = bdl_pos_adj[chip->dev_index]; 1089 pos_adj = bdl_pos_adj[chip->dev_index];
1093 if (pos_adj > 0) { 1090 if (pos_adj > 0) {
1094 struct snd_pcm_runtime *runtime = substream->runtime; 1091 struct snd_pcm_runtime *runtime = substream->runtime;
@@ -1109,7 +1106,6 @@ static int azx_setup_periods(struct azx *chip,
1109 &bdl, ofs, pos_adj, 1); 1106 &bdl, ofs, pos_adj, 1);
1110 if (ofs < 0) 1107 if (ofs < 0)
1111 goto error; 1108 goto error;
1112 azx_dev->irq_ignore = 1;
1113 } 1109 }
1114 } else 1110 } else
1115 pos_adj = 0; 1111 pos_adj = 0;
@@ -1155,6 +1151,9 @@ static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1155 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1151 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1156 --timeout) 1152 --timeout)
1157 ; 1153 ;
1154
1155 /* reset first position - may not be synced with hw at this time */
1156 *azx_dev->posbuf = 0;
1158} 1157}
1159 1158
1160/* 1159/*
@@ -1409,7 +1408,6 @@ static int azx_pcm_open(struct snd_pcm_substream *substream)
1409 snd_pcm_set_sync(substream); 1408 snd_pcm_set_sync(substream);
1410 mutex_unlock(&chip->open_mutex); 1409 mutex_unlock(&chip->open_mutex);
1411 1410
1412 azx_stream_reset(chip, azx_dev);
1413 return 0; 1411 return 0;
1414} 1412}
1415 1413
@@ -1474,6 +1472,7 @@ static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1474 unsigned int bufsize, period_bytes, format_val; 1472 unsigned int bufsize, period_bytes, format_val;
1475 int err; 1473 int err;
1476 1474
1475 azx_stream_reset(chip, azx_dev);
1477 format_val = snd_hda_calc_stream_format(runtime->rate, 1476 format_val = snd_hda_calc_stream_format(runtime->rate,
1478 runtime->channels, 1477 runtime->channels,
1479 runtime->format, 1478 runtime->format,
@@ -1502,6 +1501,8 @@ static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1502 return err; 1501 return err;
1503 } 1502 }
1504 1503
1504 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1505 (runtime->rate * 2);
1505 azx_setup_controller(chip, azx_dev); 1506 azx_setup_controller(chip, azx_dev);
1506 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1507 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1507 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; 1508 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
@@ -1518,13 +1519,14 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1518 struct azx *chip = apcm->chip; 1519 struct azx *chip = apcm->chip;
1519 struct azx_dev *azx_dev; 1520 struct azx_dev *azx_dev;
1520 struct snd_pcm_substream *s; 1521 struct snd_pcm_substream *s;
1521 int start, nsync = 0, sbits = 0; 1522 int rstart = 0, start, nsync = 0, sbits = 0;
1522 int nwait, timeout; 1523 int nwait, timeout;
1523 1524
1524 switch (cmd) { 1525 switch (cmd) {
1526 case SNDRV_PCM_TRIGGER_START:
1527 rstart = 1;
1525 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1528 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1526 case SNDRV_PCM_TRIGGER_RESUME: 1529 case SNDRV_PCM_TRIGGER_RESUME:
1527 case SNDRV_PCM_TRIGGER_START:
1528 start = 1; 1530 start = 1;
1529 break; 1531 break;
1530 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1532 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
@@ -1554,6 +1556,10 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1554 if (s->pcm->card != substream->pcm->card) 1556 if (s->pcm->card != substream->pcm->card)
1555 continue; 1557 continue;
1556 azx_dev = get_azx_dev(s); 1558 azx_dev = get_azx_dev(s);
1559 if (rstart) {
1560 azx_dev->start_flag = 1;
1561 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1562 }
1557 if (start) 1563 if (start)
1558 azx_stream_start(chip, azx_dev); 1564 azx_stream_start(chip, azx_dev);
1559 else 1565 else
@@ -1703,6 +1709,11 @@ static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1703{ 1709{
1704 unsigned int pos; 1710 unsigned int pos;
1705 1711
1712 if (azx_dev->start_flag &&
1713 time_before_eq(jiffies, azx_dev->start_jiffies))
1714 return -1; /* bogus (too early) interrupt */
1715 azx_dev->start_flag = 0;
1716
1706 pos = azx_get_position(chip, azx_dev); 1717 pos = azx_get_position(chip, azx_dev);
1707 if (chip->position_fix == POS_FIX_AUTO) { 1718 if (chip->position_fix == POS_FIX_AUTO) {
1708 if (!pos) { 1719 if (!pos) {
@@ -2260,11 +2271,11 @@ static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2260 gcap &= ~0x01; 2271 gcap &= ~0x01;
2261 2272
2262 /* allow 64bit DMA address if supported by H/W */ 2273 /* allow 64bit DMA address if supported by H/W */
2263 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK)) 2274 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2264 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK); 2275 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2265 else { 2276 else {
2266 pci_set_dma_mask(pci, DMA_32BIT_MASK); 2277 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2267 pci_set_consistent_dma_mask(pci, DMA_32BIT_MASK); 2278 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2268 } 2279 }
2269 2280
2270 /* read number of streams from GCAP register instead of using 2281 /* read number of streams from GCAP register instead of using