litmus-rt.git - The LITMUS^RT kernel.

diff options

author	Christoph Lameter <clameter@sgi.com>	2006-03-29 01:54:38 -0500
committer	Tony Luck <tony.luck@intel.com>	2006-04-08 02:08:16 -0400
commit	0ffe984917b9cd6ecc19ffbc06f35869d8c18df8 (patch)
tree	49b54ea585dcd657083c8b755726820b002ae75a /net/tipc/ref.c
parent	8cab7ccccbdd9fe3cf6b3400d5a88ecb683a5b1b (diff)

[IA64] Prefetch mmap_sem in ia64_do_page_fault()

Take a hint from an x86_64 optimization by Arjan van de Ven and use it for ia64. See a9ba9a3b3897561d01e04cd21433746df46548c0 Prefetch the mmap_sem, which is critical for the performance of the page fault handler. Note: mm may be NULL but I guess that is safe. See 458f935527372499b714bf4f8e646a68bb0f52e3 Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>

Diffstat (limited to 'net/tipc/ref.c')

0 files changed, 0 insertions, 0 deletions

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217

218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278

279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493

494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548

568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656

657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713

/* * t19x-nvlink-endpt-ioctl.c: * This file adds various IOCTLs for the Tegra NVLINK controller. * * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/uaccess.h> #include <linux/clk.h> #include "t19x-nvlink-endpt.h" #include "nvlink-hw.h" #include "tegra-nvlink-mods.h" static bool is_nvlink_loopback_topology(struct nvlink_device *ndev) { struct nvlink_link *link = &ndev->link; if (link->device_id == NVLINK_ENDPT_T19X && link->remote_dev_info.device_id == NVLINK_ENDPT_T19X) return true; return false; } static int t19x_nvlink_get_caps(struct nvlink_device *ndev, struct nvlink_caps *caps) { if (is_nvlink_loopback_topology(ndev)) { caps->nvlink_caps |= (TEGRA_CTRL_NVLINK_CAPS_SUPPORTED | TEGRA_CTRL_NVLINK_CAPS_VALID); } else { /* TODO: */ } /* Sysmem atomics are supported for NVLINK versions > 1.0 */ if (NVLINK_IP_VERSION > NVLINK_VERSION_10) caps->nvlink_caps |= TEGRA_CTRL_NVLINK_CAPS_SYSMEM_ATOMICS; switch (NVLINK_IP_VERSION) { case NVLINK_VERSION_22: caps->lowest_nvlink_version = TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2; caps->highest_nvlink_version = TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2; caps->lowest_nci_version = TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_2_2; caps->highest_nci_version = TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_2_2; /* Supported power states */ caps->nvlink_caps |= TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L0; caps->nvlink_caps |= TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L2; break; case NVLINK_VERSION_20: caps->lowest_nvlink_version = TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0; caps->highest_nvlink_version = TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0; caps->lowest_nci_version = TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_2_0; caps->highest_nci_version = TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_2_0; /* Supported power states */ caps->nvlink_caps |= TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L0; break; default: caps->lowest_nvlink_version = TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0; caps->highest_nvlink_version = TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0; caps->lowest_nci_version = TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_1_0; caps->highest_nci_version = TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_1_0; /* Supported power states */ caps->nvlink_caps |= TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L0; break; } caps->enabled_link_mask = BIT(0); caps->discovered_link_mask = BIT(0); return 0; } static int t19x_nvlink_get_status(struct nvlink_device *ndev, struct nvlink_status *status) { struct tegra_nvlink_device *tdev = ndev->priv; struct nvlink_link *link = &ndev->link; u32 reg_val = 0; u32 state = 0; /* * Link should be connected and in HS mode, otherwise * t19x_nvlink_endpt_open() will fail and we wouldn't be here. */ status->link_info.connected = true; status->link_info.remote_device_link_number = link->remote_dev_info.link_id; status->link_info.local_device_link_number = link->link_id; if (is_nvlink_loopback_topology(ndev)) { status->link_info.caps |= TEGRA_CTRL_NVLINK_CAPS_VALID; status->link_info.loop_property = TEGRA_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK; status->link_info.local_device_info.device_type = TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA; status->link_info.local_device_info.domain = 0; status->link_info.local_device_info.bus = 0; status->link_info.local_device_info.device = 0; status->link_info.local_device_info.function = 0; status->link_info.local_device_info.pci_device_id = 0; status->link_info.remote_device_info.device_type = status->link_info.local_device_info.device_type; status->link_info.remote_device_info.domain = status->link_info.local_device_info.domain; status->link_info.remote_device_info.bus = status->link_info.local_device_info.bus; status->link_info.remote_device_info.device = status->link_info.local_device_info.device; status->link_info.remote_device_info.function = status->link_info.local_device_info.function; status->link_info.remote_device_info.pci_device_id = status->link_info.local_device_info.pci_device_id; } else { /* TODO: Handle other topologies */ } status->enabled_link_mask = 1; status->link_info.phy_type = TEGRA_CTRL_NVLINK_STATUS_PHY_NVHS; status->link_info.sublink_width = 8; status->link_info.link_state = t19x_nvlink_get_link_state(ndev); t19x_nvlink_get_tx_sublink_state(ndev, &state); status->link_info.tx_sublink_status = (u8)state; t19x_nvlink_get_rx_sublink_state(ndev, &state); status->link_info.rx_sublink_status = (u8)state; reg_val = nvlw_nvl_readl(ndev, NVL_SL1_CONFIG_RX); if (reg_val & BIT(NVL_SL1_CONFIG_RX_REVERSAL_OVERRIDE)) { /* Overridden */ if (reg_val & BIT(NVL_SL1_CONFIG_RX_LANE_REVERSE)) status->link_info.bLane_reversal = true; else status->link_info.bLane_reversal = false; } else { /* Sensed in HW */ if (reg_val & BIT(NVL_SL1_CONFIG_RX_HW_LANE_REVERSE)) status->link_info.bLane_reversal = true; else status->link_info.bLane_reversal = false; } switch (NVLINK_IP_VERSION) { case NVLINK_VERSION_22: status->link_info.nvlink_version = TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2; status->link_info.nci_version = TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_2_2; break; case NVLINK_VERSION_20: status->link_info.nvlink_version = TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0; status->link_info.nci_version = TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_2_0; break; default: status->link_info.nvlink_version = TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0; status->link_info.nci_version = TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_1_0; break; } status->link_info.phy_version = TEGRA_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0; /* TODO: Change nvlink_link_clockKHz after having correct INITPLL */ status->link_info.nvlink_link_clockKHz = 24750000; status->link_info.nvlink_ref_clk_speedKHz = clk_get_rate(tdev->clk_pllnvhs) / 1000; status->link_info.nvlink_common_clock_speedKHz = status->link_info.nvlink_link_clockKHz / 16; status->link_info.nvlink_link_clockMhz = status->link_info.nvlink_link_clockKHz / 1000; status->link_info.nvlink_ref_clk_speedMhz = status->link_info.nvlink_ref_clk_speedKHz / 1000; status->link_info.nvlink_common_clock_speedMhz = status->link_info.nvlink_common_clock_speedKHz / 1000; status->link_info.nvlink_ref_clk_type = TEGRA_CTRL_NVLINK_REFCLK_TYPE_NVHS; return 0; } static int t19x_nvlink_clear_counters(struct nvlink_device *ndev, struct nvlink_clear_counters *clear_counters) { u32 reg_val = 0; u32 counter_mask = clear_counters->counter_mask; if ((counter_mask) & (TEGRA_CTRL_NVLINK_COUNTER_TL_TX0 | TEGRA_CTRL_NVLINK_COUNTER_TL_TX1 | TEGRA_CTRL_NVLINK_COUNTER_TL_RX0 | TEGRA_CTRL_NVLINK_COUNTER_TL_RX1)) { reg_val = nvlw_nvltlc_readl(ndev, NVLTLC_TX_DEBUG_TP_CNTR_CTRL); if (counter_mask & TEGRA_CTRL_NVLINK_COUNTER_TL_TX0) reg_val |= BIT(NVLTLC_TX_DEBUG_TP_CNTR_CTRL_RESETTX0); if (counter_mask & TEGRA_CTRL_NVLINK_COUNTER_TL_TX1) reg_val |= BIT(NVLTLC_TX_DEBUG_TP_CNTR_CTRL_RESETTX1); nvlw_nvltlc_writel(ndev, NVLTLC_TX_DEBUG_TP_CNTR_CTRL, reg_val); reg_val = nvlw_nvltlc_readl(ndev, NVLTLC_RX_DEBUG_TP_CNTR_CTRL); if (counter_mask & TEGRA_CTRL_NVLINK_COUNTER_TL_RX0) reg_val |= BIT(NVLTLC_RX_DEBUG_TP_CNTR_CTRL_RESETRX0); if (counter_mask & TEGRA_CTRL_NVLINK_COUNTER_TL_RX1) reg_val |= BIT(NVLTLC_RX_DEBUG_TP_CNTR_CTRL_RESETRX1); nvlw_nvltlc_writel(ndev, NVLTLC_RX_DEBUG_TP_CNTR_CTRL, reg_val); } if ((counter_mask) & (TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 | TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 | TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 | TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 | TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 | TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 | TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 | TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7)) { reg_val = nvlw_nvl_readl(ndev, NVL_SL1_ERROR_COUNT_CTRL); reg_val |= BIT(NVL_SL1_ERROR_COUNT_CTRL_CLEAR_LANE_CRC); reg_val |= BIT(NVL_SL1_ERROR_COUNT_CTRL_CLEAR_RATES); nvlw_nvl_writel(ndev, NVL_SL1_ERROR_COUNT_CTRL, reg_val); } if (counter_mask & TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT) { reg_val = nvlw_nvl_readl(ndev, NVL_SL1_ERROR_COUNT_CTRL); reg_val |= BIT(NVL_SL1_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC); reg_val |= BIT(NVL_SL1_ERROR_COUNT_CTRL_CLEAR_RATES); nvlw_nvl_writel(ndev, NVL_SL1_ERROR_COUNT_CTRL, reg_val); } if (counter_mask & TEGRA_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY) { reg_val = nvlw_nvl_readl(ndev, NVL_SL0_ERROR_COUNT_CTRL); reg_val |= BIT(NVL_SL0_ERROR_COUNT_CTRL_CLEAR_REPLAY); nvlw_nvl_writel(ndev, NVL_SL0_ERROR_COUNT_CTRL, reg_val); } if (counter_mask & TEGRA_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY) { reg_val = nvlw_nvl_readl(ndev, NVL_ERROR_COUNT_CTRL); reg_val |= BIT(NVL_ERROR_COUNT_CTRL_CLEAR_RECOVERY); nvlw_nvl_writel(ndev, NVL_ERROR_COUNT_CTRL, reg_val); } return 0; } static bool t19x_nvlink_is_lane_reversal(struct nvlink_device *ndev) { u32 reg_val; bool lane_reversal; reg_val = nvlw_nvl_readl(ndev, NVL_SL1_CONFIG_RX); if (reg_val & BIT(NVL_SL1_CONFIG_RX_REVERSAL_OVERRIDE)) { if (reg_val & BIT(NVL_SL1_CONFIG_RX_LANE_REVERSE)) lane_reversal = true; else lane_reversal = false; } else { if (reg_val & BIT(NVL_SL1_CONFIG_RX_HW_LANE_REVERSE)) lane_reversal = true; else lane_reversal = false; } return lane_reversal; } static void t19x_nvlink_get_lane_crc_errors(struct nvlink_device *ndev, struct nvlink_get_counters *get_counters) { int i; int lane_id; u32 reg_val; u64 lane_crc_val; u32 counter_mask = get_counters->counter_mask; for (i = 0; i < TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_SIZE; i++) { if (counter_mask & TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(i)) { lane_id = i; if (t19x_nvlink_is_lane_reversal(ndev)) lane_id = 7 - lane_id; if (lane_id < 4) { reg_val = nvlw_nvl_readl(ndev, NVL_SL1_ERROR_COUNT2_LANECRC); } else { reg_val = nvlw_nvl_readl(ndev, NVL_SL1_ERROR_COUNT3_LANECRC); } switch (lane_id) { case 0: lane_crc_val = (u64) NVL_SL1_ERROR_COUNT2_LANECRC_L0_V( reg_val); get_counters->nvlink_counters[ nvlink_counter(i)] = lane_crc_val; break; case 1: lane_crc_val = (u64) NVL_SL1_ERROR_COUNT2_LANECRC_L1_V( reg_val); get_counters->nvlink_counters[ nvlink_counter(i)] = lane_crc_val; break; case 2: lane_crc_val = (u64) NVL_SL1_ERROR_COUNT2_LANECRC_L2_V( reg_val); get_counters->nvlink_counters[ nvlink_counter(i)] = lane_crc_val; break; case 3: lane_crc_val = (u64) NVL_SL1_ERROR_COUNT2_LANECRC_L3_V( reg_val); get_counters->nvlink_counters[ nvlink_counter(i)] = lane_crc_val; break; case 4: lane_crc_val = (u64) NVL_SL1_ERROR_COUNT3_LANECRC_L4_V( reg_val); get_counters->nvlink_counters[ nvlink_counter(i)] = lane_crc_val; break; case 5: lane_crc_val = (u64) NVL_SL1_ERROR_COUNT3_LANECRC_L5_V( reg_val); get_counters->nvlink_counters[ nvlink_counter(i)] = lane_crc_val; break; case 6: lane_crc_val = (u64) NVL_SL1_ERROR_COUNT3_LANECRC_L6_V( reg_val); get_counters->nvlink_counters[ nvlink_counter(i)] = lane_crc_val; break; case 7: lane_crc_val = (u64) NVL_SL1_ERROR_COUNT3_LANECRC_L7_V( reg_val); get_counters->nvlink_counters[ nvlink_counter(i)] = lane_crc_val; break; default: break; } }


context:
space:
mode: