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authorRuchika Gupta <ruchika.gupta@freescale.com>2014-06-23 05:38:28 -0400
committerHerbert Xu <herbert@gondor.apana.org.au>2014-06-25 09:38:39 -0400
commiteb1139cd437afadc63f58159c111e3f166bddb51 (patch)
tree4999c51729b5cd22f4485695b2d89fb873c784b2 /net/mac802154/Kconfig
parente60b244281cfe03ddd7c5c15c4e6b6d6316bb530 (diff)
crypto: caam - Correct definition of registers in memory map
Some registers like SECVID, CHAVID, CHA Revision Number, CTPR were defined as 64 bit resgisters. The IP provides a DWT bit(Double word Transpose) to transpose the two words when a double word register is accessed. However setting this bit would also affect the operation of job descriptors as well as other registers which are truly double word in nature. So, for the IP to work correctly on big-endian as well as little-endian SoC's, change is required to access all 32 bit registers as 32 bit quantities. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'net/mac802154/Kconfig')
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