genirq: Generic chip: Add big endian I/O accessors

Use io{read,write}32be if the caller specified IRQ_GC_BE_IO when creating
the irqchip.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/1415342669-30640-5-git-send-email-cernekee@gmail.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

1 files changed, 16 insertions, 0 deletions

diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index db458c68e392..61024e8abdef 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -191,6 +191,16 @@ int irq_gc_set_wake(struct irq_data *d, unsigned int on)
         return 0;
 }
 
+static u32 irq_readl_be(void __iomem *addr)
+{
+        return ioread32be(addr);
+}
+
+static void irq_writel_be(u32 val, void __iomem *addr)
+{
+        iowrite32be(val, addr);
+}
+
 static void
 irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
                       int num_ct, unsigned int irq_base,
@@ -300,7 +310,13 @@ int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
                 dgc->gc[i] = gc = tmp;
                 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
                                       NULL, handler);
+
                 gc->domain = d;
+                if (gcflags & IRQ_GC_BE_IO) {
+                        gc->reg_readl = &irq_readl_be;
+                        gc->reg_writel = &irq_writel_be;
+                }
+
                 raw_spin_lock_irqsave(&gc_lock, flags);
                 list_add_tail(&gc->list, &gc_list);
                 raw_spin_unlock_irqrestore(&gc_lock, flags);