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authorThomas Gleixner <tglx@linutronix.de>2013-06-28 05:45:15 -0400
committerThomas Gleixner <tglx@linutronix.de>2013-06-28 06:56:04 -0400
commitccc414f83914178c7ab04ac4d4f0331fe4c37231 (patch)
treebb4ec23371f397de9407b4854e287e3c5d08efb5 /kernel/irq
parentd55f0cc4c9a70e3105f1e813ab5f221a65ac2ec3 (diff)
genirq: Add the generic chip to the genirq docbook
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Randy Dunlap <rdunlap@infradead.org>
Diffstat (limited to 'kernel/irq')
-rw-r--r--kernel/irq/generic-chip.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index 76ea748324f5..1c39eccc1eaf 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -45,7 +45,7 @@ void irq_gc_mask_disable_reg(struct irq_data *d)
45} 45}
46 46
47/** 47/**
48 * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register 48 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
49 * @d: irq_data 49 * @d: irq_data
50 * 50 *
51 * Chip has a single mask register. Values of this register are cached 51 * Chip has a single mask register. Values of this register are cached
@@ -65,7 +65,7 @@ void irq_gc_mask_set_bit(struct irq_data *d)
65EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit); 65EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
66 66
67/** 67/**
68 * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register 68 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
69 * @d: irq_data 69 * @d: irq_data
70 * 70 *
71 * Chip has a single mask register. Values of this register are cached 71 * Chip has a single mask register. Values of this register are cached
@@ -167,7 +167,8 @@ void irq_gc_eoi(struct irq_data *d)
167 167
168/** 168/**
169 * irq_gc_set_wake - Set/clr wake bit for an interrupt 169 * irq_gc_set_wake - Set/clr wake bit for an interrupt
170 * @d: irq_data 170 * @d: irq_data
171 * @on: Indicates whether the wake bit should be set or cleared
171 * 172 *
172 * For chips where the wake from suspend functionality is not 173 * For chips where the wake from suspend functionality is not
173 * configured in a separate register and the wakeup active state is 174 * configured in a separate register and the wakeup active state is
@@ -339,7 +340,7 @@ EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
339 */ 340 */
340static struct lock_class_key irq_nested_lock_class; 341static struct lock_class_key irq_nested_lock_class;
341 342
342/** 343/*
343 * irq_map_generic_chip - Map a generic chip for an irq domain 344 * irq_map_generic_chip - Map a generic chip for an irq domain
344 */ 345 */
345static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 346static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
@@ -454,7 +455,7 @@ EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
454/** 455/**
455 * irq_setup_alt_chip - Switch to alternative chip 456 * irq_setup_alt_chip - Switch to alternative chip
456 * @d: irq_data for this interrupt 457 * @d: irq_data for this interrupt
457 * @type Flow type to be initialized 458 * @type: Flow type to be initialized
458 * 459 *
459 * Only to be called from chip->irq_set_type() callbacks. 460 * Only to be called from chip->irq_set_type() callbacks.
460 */ 461 */