litmus-rt.git - The LITMUS^RT kernel.

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author	Stephen Warren <swarren@nvidia.com>	2011-12-19 14:24:04 -0500
committer	Olof Johansson <olof@lixom.net>	2011-12-19 21:06:27 -0500
commit	24692c0fc6ee62b1b98dfab962694ca40a3e404a (patch)
tree	f0983bdf79d5ef33068c19d61fdcb52efb67ee81 /kernel/extable.c
parent	229f05fdb025ff82f47221c11ee5dfa73f7e4cb2 (diff)

arm/tegra: Make MACH_TEGRA_DT depend on ARCH_TEGRA_2x_SOC

Now that Tegra20 and Tegra30 device tree board files are separate, MACH_TEGRA_DT (which enables the Tegra20 device tree board file) should depend on Tegra20 support being enabled. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>

Diffstat (limited to 'kernel/extable.c')

0 files changed, 0 insertions, 0 deletions

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/* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, version 2, as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * Copyright (C) 2013 Freescale Semiconductor, Inc. * */ #define pr_fmt(fmt) "fsl-pamu: %s: " fmt, __func__ #include <linux/init.h> #include <linux/iommu.h> #include <linux/slab.h> #include <linux/module.h> #include <linux/types.h> #include <linux/mm.h> #include <linux/interrupt.h> #include <linux/device.h> #include <linux/of_platform.h> #include <linux/bootmem.h> #include <linux/genalloc.h> #include <asm/io.h> #include <asm/bitops.h> #include <asm/fsl_guts.h> #include "fsl_pamu.h" /* define indexes for each operation mapping scenario */ #define OMI_QMAN 0x00 #define OMI_FMAN 0x01 #define OMI_QMAN_PRIV 0x02 #define OMI_CAAM 0x03 #define make64(high, low) (((u64)(high) << 32) | (low)) struct pamu_isr_data { void __iomem *pamu_reg_base; /* Base address of PAMU regs*/ unsigned int count; /* The number of PAMUs */ }; static struct paace *ppaact; static struct paace *spaact; static struct ome *omt; /* * Table for matching compatible strings, for device tree * guts node, for QorIQ SOCs. * "fsl,qoriq-device-config-2.0" corresponds to T4 & B4 * SOCs. For the older SOCs "fsl,qoriq-device-config-1.0" * string would be used. */ static const struct of_device_id guts_device_ids[] = { { .compatible = "fsl,qoriq-device-config-1.0", }, { .compatible = "fsl,qoriq-device-config-2.0", }, {} }; /* * Table for matching compatible strings, for device tree * L3 cache controller node. * "fsl,t4240-l3-cache-controller" corresponds to T4, * "fsl,b4860-l3-cache-controller" corresponds to B4 & * "fsl,p4080-l3-cache-controller" corresponds to other, * SOCs. */ static const struct of_device_id l3_device_ids[] = { { .compatible = "fsl,t4240-l3-cache-controller", }, { .compatible = "fsl,b4860-l3-cache-controller", }, { .compatible = "fsl,p4080-l3-cache-controller", }, {} }; /* maximum subwindows permitted per liodn */ static u32 max_subwindow_count; /* Pool for fspi allocation */ struct gen_pool *spaace_pool; /** * pamu_get_max_subwin_cnt() - Return the maximum supported * subwindow count per liodn. * */ u32 pamu_get_max_subwin_cnt() { return max_subwindow_count; } /** * pamu_get_ppaace() - Return the primary PACCE * @liodn: liodn PAACT index for desired PAACE * * Returns the ppace pointer upon success else return * null. */ static struct paace *pamu_get_ppaace(int liodn) { if (!ppaact || liodn >= PAACE_NUMBER_ENTRIES) { pr_debug("PPAACT doesn't exist\n"); return NULL; } return &ppaact[liodn]; } /** * pamu_enable_liodn() - Set valid bit of PACCE * @liodn: liodn PAACT index for desired PAACE * * Returns 0 upon success else error code < 0 returned */ int pamu_enable_liodn(int liodn) { struct paace *ppaace; ppaace = pamu_get_ppaace(liodn); if (!ppaace) { pr_debug("Invalid primary paace entry\n"); return -ENOENT; } if (!get_bf(ppaace->addr_bitfields, PPAACE_AF_WSE)) { pr_debug("liodn %d not configured\n", liodn); return -EINVAL; } /* Ensure that all other stores to the ppaace complete first */ mb(); set_bf(ppaace->addr_bitfields, PAACE_AF_V, PAACE_V_VALID); mb(); return 0; } /** * pamu_disable_liodn() - Clears valid bit of PACCE * @liodn: liodn PAACT index for desired PAACE * * Returns 0 upon success else error code < 0 returned */ int pamu_disable_liodn(int liodn) { struct paace *ppaace; ppaace = pamu_get_ppaace(liodn); if (!ppaace) { pr_debug("Invalid primary paace entry\n"); return -ENOENT; } set_bf(ppaace->addr_bitfields, PAACE_AF_V, PAACE_V_INVALID); mb(); return 0; } /* Derive the window size encoding for a particular PAACE entry */ static unsigned int map_addrspace_size_to_wse(phys_addr_t addrspace_size) { /* Bug if not a power of 2 */ BUG_ON(!is_power_of_2(addrspace_size)); /* window size is 2^(WSE+1) bytes */ return __ffs(addrspace_size) - 1; } /* Derive the PAACE window count encoding for the subwindow count */ static unsigned int map_subwindow_cnt_to_wce(u32 subwindow_cnt) { /* window count is 2^(WCE+1) bytes */ return __ffs(subwindow_cnt) - 1; } /* * Set the PAACE type as primary and set the coherency required domain * attribute */ static void pamu_init_ppaace(struct paace *ppaace) { set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY); set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR, PAACE_M_COHERENCE_REQ); } /* * Set the PAACE type as secondary and set the coherency required domain * attribute. */ static void pamu_init_spaace(struct paace *spaace) { set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY); set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR, PAACE_M_COHERENCE_REQ); } /* * Return the spaace (corresponding to the secondary window index) * for a particular ppaace. */ static struct paace *pamu_get_spaace(struct paace *paace, u32 wnum) { u32 subwin_cnt; struct paace *spaace = NULL; subwin_cnt = 1UL << (get_bf(paace->impl_attr, PAACE_IA_WCE) + 1); if (wnum < subwin_cnt) spaace = &spaact[paace->fspi + wnum]; else pr_debug("secondary paace out of bounds\n"); return spaace; } /** * pamu_get_fspi_and_allocate() - Allocates fspi index and reserves subwindows * required for primary PAACE in the secondary * PAACE table. * @subwin_cnt: Number of subwindows to be reserved. * * A PPAACE entry may have a number of associated subwindows. A subwindow * corresponds to a SPAACE entry in the SPAACT table. Each PAACE entry stores * the index (fspi) of the first SPAACE entry in the SPAACT table. This * function returns the index of the first SPAACE entry. The remaining * SPAACE entries are reserved contiguously from that index. * * Returns a valid fspi index in the range of 0 - SPAACE_NUMBER_ENTRIES on success. * If no SPAACE entry is available or the allocator can not reserve the required * number of contiguous entries function returns ULONG_MAX indicating a failure. * */ static unsigned long pamu_get_fspi_and_allocate(u32 subwin_cnt) { unsigned long spaace_addr; spaace_addr = gen_pool_alloc(spaace_pool, subwin_cnt * sizeof(struct paace)); if (!spaace_addr) return ULONG_MAX; return (spaace_addr - (unsigned long)spaact) / (sizeof(struct paace)); } /* Release the subwindows reserved for a particular LIODN */ void pamu_free_subwins(int liodn) { struct paace *ppaace; u32 subwin_cnt, size; ppaace = pamu_get_ppaace(liodn); if (!ppaace) { pr_debug("Invalid liodn entry\n"); return; } if (get_bf(ppaace->addr_bitfields, PPAACE_AF_MW)) { subwin_cnt = 1UL << (get_bf(ppaace->impl_attr, PAACE_IA_WCE) + 1); size = (subwin_cnt - 1) * sizeof(struct paace); gen_pool_free(spaace_pool, (unsigned long)&spaact[ppaace->fspi], size); set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0); } } /* * Function used for updating stash destination for the coressponding * LIODN. */ int pamu_update_paace_stash(int liodn, u32 subwin, u32 value) { struct paace *paace; paace = pamu_get_ppaace(liodn); if (!paace) { pr_debug("Invalid liodn entry\n"); return -ENOENT; } if (subwin) { paace = pamu_get_spaace(paace, subwin - 1); if (!paace) { return -ENOENT; } } set_bf(paace->impl_attr, PAACE_IA_CID, value); mb(); return 0; } /* Disable a subwindow corresponding to the LIODN */ int pamu_disable_spaace(int liodn, u32 subwin) { struct paace *paace; paace = pamu_get_ppaace(liodn); if (!paace) { pr_debug("Invalid liodn entry\n"); return -ENOENT; } if (subwin) { paace = pamu_get_spaace(paace, subwin - 1); if (!paace) { return -ENOENT; } set_bf(paace->addr_bitfields, PAACE_AF_V, PAACE_V_INVALID); } else { set_bf(paace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_DENIED); } mb(); return 0; } /** * pamu_config_paace() - Sets up PPAACE entry for specified liodn * * @liodn: Logical IO device number * @win_addr: starting address of DSA window * @win-size: size of DSA window * @omi: Operation mapping index -- if ~omi == 0 then omi not defined * @rpn: real (true physical) page number * @stashid: cache stash id for associated cpu -- if ~stashid == 0 then * stashid not defined * @snoopid: snoop id for hardware coherency -- if ~snoopid == 0 then * snoopid not defined * @subwin_cnt: number of sub-windows * @prot: window permissions * * Returns 0 upon success else error code < 0 returned */ int pamu_config_ppaace(int liodn, phys_addr_t win_addr, phys_addr_t win_size, u32 omi, unsigned long rpn, u32 snoopid, u32 stashid, u32 subwin_cnt, int prot) { struct paace *ppaace; unsigned long fspi; if (!is_power_of_2(win_size) || win_size < PAMU_PAGE_SIZE) { pr_debug("window size too small or not a power of two %llx\n", win_size); return -EINVAL; } if (win_addr & (win_size - 1)) { pr_debug("window address is not aligned with window size\n"); return -EINVAL; } ppaace = pamu_get_ppaace(liodn); if (!ppaace) { return -ENOENT; } /* window size is 2^(WSE+1) bytes */ set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE, map_addrspace_size_to_wse(win_size)); pamu_init_ppaace(ppaace); ppaace->wbah = win_addr >> (PAMU_PAGE_SHIFT + 20); set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL, (win_addr >> PAMU_PAGE_SHIFT)); /* set up operation mapping if it's configured */ if (omi < OME_NUMBER_ENTRIES) { set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED); ppaace->op_encode.index_ot.omi = omi; } else if (~omi != 0) { pr_debug("bad operation mapping index: %d\n", omi); return -EINVAL; } /* configure stash id */ if (~stashid != 0) set_bf(ppaace->impl_attr, PAACE_IA_CID, stashid); /* configure snoop id */ if (~snoopid != 0) ppaace->domain_attr.to_host.snpid = snoopid; if (subwin_cnt) { /* The first entry is in the primary PAACE instead */ fspi = pamu_get_fspi_and_allocate(subwin_cnt - 1); if (fspi == ULONG_MAX) { pr_debug("spaace indexes exhausted\n"); return -EINVAL; } /* window count is 2^(WCE+1) bytes */ set_bf(ppaace->impl_attr, PAACE_IA_WCE, map_subwindow_cnt_to_wce(subwin_cnt)); set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0x1); ppaace->fspi = fspi; } else { set_bf(ppaace->impl_attr, PAACE_IA_ATM, PAACE_ATM_WINDOW_XLATE); ppaace->twbah = rpn >> 20; set_bf(ppaace->win_bitfields, PAACE_WIN_TWBAL, rpn); set_bf(ppaace->addr_bitfields, PAACE_AF_AP, prot); set_bf(ppaace->impl_attr, PAACE_IA_WCE, 0); set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0); } mb(); return 0; } /** * pamu_config_spaace() - Sets up SPAACE entry for specified subwindow * * @liodn: Logical IO device number * @subwin_cnt: number of sub-windows associated with dma-window * @subwin: subwindow index * @subwin_size: size of subwindow * @omi: Operation mapping index * @rpn: real (true physical) page number * @snoopid: snoop id for hardware coherency -- if ~snoopid == 0 then * snoopid not defined * @stashid: cache stash id for associated cpu * @enable: enable/disable subwindow after reconfiguration * @prot: sub window permissions * * Returns 0 upon success else error code < 0 returned */ int pamu_config_spaace(int liodn, u32 subwin_cnt, u32 subwin, phys_addr_t subwin_size, u32 omi, unsigned long rpn, u32 snoopid, u32 stashid, int enable, int prot) { struct paace *paace; /* setup sub-windows */ if (!subwin_cnt) { pr_debug("Invalid subwindow count\n"); return -EINVAL; } paace = pamu_get_ppaace(liodn); if (subwin > 0 && subwin < subwin_cnt && paace) { paace = pamu_get_spaace(paace, subwin - 1); if (paace && !(paace->addr_bitfields & PAACE_V_VALID)) { pamu_init_spaace(paace); set_bf(paace->addr_bitfields, SPAACE_AF_LIODN, liodn); } } if (!paace) { pr_debug("Invalid liodn entry\n"); return -ENOENT; } if (!is_power_of_2(subwin_size) || subwin_size < PAMU_PAGE_SIZE) { pr_debug("subwindow size out of range, or not a power of 2\n"); return -EINVAL; } if (rpn == ULONG_MAX) { pr_debug("real page number out of range\n"); return -EINVAL; } /* window size is 2^(WSE+1) bytes */ set_bf(paace->win_bitfields, PAACE_WIN_SWSE, map_addrspace_size_to_wse(subwin_size)); set_bf(paace->impl_attr, PAACE_IA_ATM, PAACE_ATM_WINDOW_XLATE); paace->twbah = rpn >> 20; set_bf(paace->win_bitfields, PAACE_WIN_TWBAL, rpn); set_bf(paace->addr_bitfields, PAACE_AF_AP, prot); /* configure snoop id */ if (~snoopid != 0) paace->domain_attr.to_host.snpid = snoopid; /* set up operation mapping if it's configured */ if (omi < OME_NUMBER_ENTRIES) { set_bf(paace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED); paace->op_encode.index_ot.omi = omi; } else if (~omi != 0) { pr_debug("bad operation mapping index: %d\n", omi); return -EINVAL; } if (~stashid != 0) set_bf(paace->impl_attr, PAACE_IA_CID, stashid); smp_wmb(); if (enable) set_bf(paace->addr_bitfields, PAACE_AF_V, PAACE_V_VALID); mb(); return 0; } /** * get_ome_index() - Returns the index in the operation mapping table * for device. * @*omi_index: pointer for storing the index value


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