litmus-rt.git - The LITMUS^RT kernel.

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author	Laurent Pinchart <laurent.pinchart@ideasonboard.com>	2012-07-06 07:41:25 -0400
committer	Mauro Carvalho Chehab <mchehab@redhat.com>	2012-07-06 18:36:39 -0400
commit	5aedc1094041335598c6aa73c5cf882f30886cd7 (patch)
tree	bfbc23e4ca5ae706d0e424e118a5973dd99d1a7c /kernel/cpu_pm.c
parent	7103180b4385de908d69815dbd6807879d371cbf (diff)

[media] omap3isp: preview: Fix contrast and brightness handling

Commit bac387efbb88cf0e8df6f46a38387897cea464ee ("omap3isp: preview: Simplify configuration parameters access") added three fields to the preview_update structure, but failed to properly update the related initializers. Fix this. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

Diffstat (limited to 'kernel/cpu_pm.c')

0 files changed, 0 insertions, 0 deletions

/* * Broadcom specific AMBA * ChipCommon Power Management Unit driver * * Copyright 2009, Michael Buesch <m@bues.ch> * Copyright 2007, 2011, Broadcom Corporation * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> * * Licensed under the GNU/GPL. See COPYING for details. */ #include "bcma_private.h" #include <linux/export.h> #include <linux/bcma/bcma.h> u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) { bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); } EXPORT_SYMBOL_GPL(bcma_chipco_pll_read); void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value) { bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value); } EXPORT_SYMBOL_GPL(bcma_chipco_pll_write); void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, u32 set) { bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set); } EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset); void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, u32 set) { bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset); bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR); bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set); } EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset); void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, u32 set) { bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset); bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR); bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set); } EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset); static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc) { u32 ilp_ctl, alp_hz; if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) & BCMA_CC_PMU_STAT_EXT_LPO_AVAIL)) return 0; bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT)); usleep_range(1000, 2000); ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ); ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK; bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0); alp_hz = ilp_ctl * 32768 / 4; return (alp_hz + 50000) / 100000 * 100; } static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq) { struct bcma_bus *bus = cc->core->bus; u32 freq_tgt_target = 0, freq_tgt_current; u32 pll0, mask; switch (bus->chipinfo.id) { case BCMA_CHIP_ID_BCM43142: /* pmu2_xtaltab0_adfll_485 */ switch (xtalfreq) { case 12000: freq_tgt_target = 0x50D52; break; case 20000: freq_tgt_target = 0x307FE; break; case 26000: freq_tgt_target = 0x254EA; break; case 37400: freq_tgt_target = 0x19EF8; break; case 52000: freq_tgt_target = 0x12A75; break; } break; } if (!freq_tgt_target) { bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n", xtalfreq); return; } pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; if (freq_tgt_current == freq_tgt_target) { bcma_debug(bus, "Target TGT frequency already set\n"); return; } /* Turn off PLL */ switch (bus->chipinfo.id) { case BCMA_CHIP_ID_BCM43142: mask = (u32)~(BCMA_RES_4314_HT_AVAIL | BCMA_RES_4314_MACPHY_CLK_AVAIL); bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask); bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask); bcma_wait_value(cc->core, BCMA_CLKCTLST, BCMA_CLKCTLST_HAVEHT, 0, 20000); break; } pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); /* Flush */ if (cc->pmu.rev >= 2) bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD); /* TODO: Do we need to update OTP? */ } static void bcma_pmu_pll_init(struct bcma_drv_cc *cc) { struct bcma_bus *bus = cc->core->bus; u32 xtalfreq = bcma_pmu_xtalfreq(cc); switch (bus->chipinfo.id) { case BCMA_CHIP_ID_BCM43142: if (xtalfreq == 0) xtalfreq = 20000; bcma_pmu2_pll_init0(cc, xtalfreq); break; } } static void bcma_pmu_resources_init(struct bcma_drv_cc *cc) { struct bcma_bus *bus = cc->core->bus; u32 min_msk = 0, max_msk = 0; switch (bus->chipinfo.id) { case BCMA_CHIP_ID_BCM4313: min_msk = 0x200D; max_msk = 0xFFFF; break; case BCMA_CHIP_ID_BCM43142: min_msk = BCMA_RES_4314_LPLDO_PU | BCMA_RES_4314_PMU_SLEEP_DIS | BCMA_RES_4314_PMU_BG_PU | BCMA_RES_4314_CBUCK_LPOM_PU | BCMA_RES_4314_CBUCK_PFM_PU | BCMA_RES_4314_CLDO_PU | BCMA_RES_4314_LPLDO2_LVM | BCMA_RES_4314_WL_PMU_PU | BCMA_RES_4314_LDO3P3_PU | BCMA_RES_4314_OTP_PU | BCMA_RES_4314_WL_PWRSW_PU | BCMA_RES_4314_LQ_AVAIL | BCMA_RES_4314_LOGIC_RET | BCMA_RES_4314_MEM_SLEEP | BCMA_RES_4314_MACPHY_RET | BCMA_RES_4314_WL_CORE_READY; max_msk = 0x3FFFFFFF; break; default: bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n", bus->chipinfo.id); } /* Set the resource masks. */ if (min_msk) bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk); if (max_msk) bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk); /* * Add some delay; allow resources to come up and settle. * Delay is required for SoC (early init). */ mdelay(2); } /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */ void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable) { struct bcma_bus *bus = cc->core->bus; u32 val; val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL); if (enable) { val |= BCMA_CHIPCTL_4331_EXTPA_EN; if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11) val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; else if (bus->chipinfo.rev > 0) val |= BCMA_CHIPCTL_4331_EXTPA_EN2; } else { val &= ~BCMA_CHIPCTL_4331_EXTPA_EN; val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2; val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; } bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val); } static void bcma_pmu_workarounds(struct bcma_drv_cc *cc) { struct bcma_bus *bus = cc->core->bus; switch (bus->chipinfo.id) { case BCMA_CHIP_ID_BCM4313: /* enable 12 mA drive strenth for 4313 and set chipControl register bit 1 */ bcma_chipco_chipctl_maskset(cc, 0, ~BCMA_CCTRL_4313_12MA_LED_DRIVE, BCMA_CCTRL_4313_12MA_LED_DRIVE); break; case BCMA_CHIP_ID_BCM4331: case BCMA_CHIP_ID_BCM43431: /* Ext PA lines must be enabled for tx on BCM4331 */ bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true); break; case BCMA_CHIP_ID_BCM43224: case BCMA_CHIP_ID_BCM43421: /* enable 12 mA drive strenth for 43224 and set chipControl register bit 15 */ if (bus->chipinfo.rev == 0) { bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL, ~BCMA_CCTRL_43224_GPIO_TOGGLE, BCMA_CCTRL_43224_GPIO_TOGGLE); bcma_chipco_chipctl_maskset(cc, 0, ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE, BCMA_CCTRL_43224A0_12MA_LED_DRIVE); } else { bcma_chipco_chipctl_maskset(cc, 0, ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE, BCMA_CCTRL_43224B0_12MA_LED_DRIVE); } break; default: bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n", bus->chipinfo.id); } } void bcma_pmu_early_init(struct bcma_drv_cc *cc) { u32 pmucap; pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);


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