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authorDave Airlie <airlied@redhat.com>2015-01-20 19:17:16 -0500
committerDave Airlie <airlied@redhat.com>2015-01-20 19:17:16 -0500
commitfc83975348ebce07793e6b9f780edc3cbcffa9fc (patch)
tree0fc7972c181cebed1c344852bb8b1a96607d3b15 /include
parentb2eb0489809cf0b824357b6fa85aab1aabe3f063 (diff)
parentd50141d8072e5322ee0518a8c967b5c9caf463d2 (diff)
Merge tag 'imx-drm-next-2015-01-09' of git://git.pengutronix.de/git/pza/linux into drm-next
imx-drm mode fixup support, imx-hdmi bridge conversion and imx-drm cleanup - Implement mode_fixup for a DI vertical timing limitation - Use generic DRM OF helpers in DRM core - Convert imx-hdmi to dw_hdmi drm_bridge and add rockchip driver - Add DC use counter to fix multi-display support - Simplify handling of DI clock flags - A few small fixes and cleanup * tag 'imx-drm-next-2015-01-09' of git://git.pengutronix.de/git/pza/linux: (26 commits) imx-drm: core: handling of DI clock flags to ipu_crtc_mode_set() gpu: ipu-di: Switch to DIV_ROUND_CLOSEST for DI clock divider calc gpu: ipu-v3: Use videomode in struct ipu_di_signal_cfg imx-drm: encoder prepare/mode_set must use adjusted mode imx-drm: ipuv3-crtc: Implement mode_fixup drm_modes: add drm_display_mode_to_videomode gpu: ipu-di: remove some non-functional code gpu: ipu-di: Add ipu_di_adjust_videomode() drm: rockchip: export functions needed by rockchip dw_hdmi bridge driver drm: bridge/dw_hdmi: request interrupt only after initializing the mutes drm: bridge/dw_hdmi: add rockchip rk3288 support dt-bindings: Add documentation for rockchip dw hdmi drm: bridge/dw_hdmi: add function dw_hdmi_phy_enable_spare drm: bridge/dw_hdmi: clear i2cmphy_stat0 reg in hdmi_phy_wait_i2c_done drm: bridge/dw_hdmi: add mode_valid support drm: bridge/dw_hdmi: add support for multi-byte register width access dt-bindings: add document for dw_hdmi drm: imx: imx-hdmi: move imx-hdmi to bridge/dw_hdmi drm: imx: imx-hdmi: split phy configuration to platform driver drm: imx: imx-hdmi: convert imx-hdmi to drm_bridge mode ...
Diffstat (limited to 'include')
-rw-r--r--include/drm/bridge/dw_hdmi.h61
-rw-r--r--include/drm/drm_modes.h2
-rw-r--r--include/video/imx-ipu-v3.h21
3 files changed, 68 insertions, 16 deletions
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
new file mode 100644
index 000000000000..5a4f49005169
--- /dev/null
+++ b/include/drm/bridge/dw_hdmi.h
@@ -0,0 +1,61 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DW_HDMI__
11#define __DW_HDMI__
12
13#include <drm/drmP.h>
14
15enum {
16 DW_HDMI_RES_8,
17 DW_HDMI_RES_10,
18 DW_HDMI_RES_12,
19 DW_HDMI_RES_MAX,
20};
21
22enum dw_hdmi_devtype {
23 IMX6Q_HDMI,
24 IMX6DL_HDMI,
25 RK3288_HDMI,
26};
27
28struct dw_hdmi_mpll_config {
29 unsigned long mpixelclock;
30 struct {
31 u16 cpce;
32 u16 gmp;
33 } res[DW_HDMI_RES_MAX];
34};
35
36struct dw_hdmi_curr_ctrl {
37 unsigned long mpixelclock;
38 u16 curr[DW_HDMI_RES_MAX];
39};
40
41struct dw_hdmi_sym_term {
42 unsigned long mpixelclock;
43 u16 sym_ctr; /*clock symbol and transmitter control*/
44 u16 term; /*transmission termination value*/
45};
46
47struct dw_hdmi_plat_data {
48 enum dw_hdmi_devtype dev_type;
49 const struct dw_hdmi_mpll_config *mpll_cfg;
50 const struct dw_hdmi_curr_ctrl *cur_ctr;
51 const struct dw_hdmi_sym_term *sym_term;
52 enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
53 struct drm_display_mode *mode);
54};
55
56void dw_hdmi_unbind(struct device *dev, struct device *master, void *data);
57int dw_hdmi_bind(struct device *dev, struct device *master,
58 void *data, struct drm_encoder *encoder,
59 struct resource *iores, int irq,
60 const struct dw_hdmi_plat_data *plat_data);
61#endif /* __IMX_HDMI_H__ */
diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
index b162ccd321f3..d92f6dd1fb11 100644
--- a/include/drm/drm_modes.h
+++ b/include/drm/drm_modes.h
@@ -200,6 +200,8 @@ struct drm_display_mode *drm_gtf_mode_complex(struct drm_device *dev,
200 int GTF_K, int GTF_2J); 200 int GTF_K, int GTF_2J);
201void drm_display_mode_from_videomode(const struct videomode *vm, 201void drm_display_mode_from_videomode(const struct videomode *vm,
202 struct drm_display_mode *dmode); 202 struct drm_display_mode *dmode);
203void drm_display_mode_to_videomode(const struct drm_display_mode *dmode,
204 struct videomode *vm);
203int of_get_drm_display_mode(struct device_node *np, 205int of_get_drm_display_mode(struct device_node *np,
204 struct drm_display_mode *dmode, 206 struct drm_display_mode *dmode,
205 int index); 207 int index);
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index c74bf4a0520e..73390c120cad 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -17,6 +17,7 @@
17#include <linux/bitmap.h> 17#include <linux/bitmap.h>
18#include <linux/fb.h> 18#include <linux/fb.h>
19#include <media/v4l2-mediabus.h> 19#include <media/v4l2-mediabus.h>
20#include <video/videomode.h>
20 21
21struct ipu_soc; 22struct ipu_soc;
22 23
@@ -32,28 +33,15 @@ enum ipuv3_type {
32 * Bitfield of Display Interface signal polarities. 33 * Bitfield of Display Interface signal polarities.
33 */ 34 */
34struct ipu_di_signal_cfg { 35struct ipu_di_signal_cfg {
35 unsigned datamask_en:1;
36 unsigned interlaced:1;
37 unsigned odd_field_first:1;
38 unsigned clksel_en:1;
39 unsigned clkidle_en:1;
40 unsigned data_pol:1; /* true = inverted */ 36 unsigned data_pol:1; /* true = inverted */
41 unsigned clk_pol:1; /* true = rising edge */ 37 unsigned clk_pol:1; /* true = rising edge */
42 unsigned enable_pol:1; 38 unsigned enable_pol:1;
43 unsigned Hsync_pol:1; /* true = active high */
44 unsigned Vsync_pol:1;
45 39
46 u16 width; 40 struct videomode mode;
47 u16 height; 41
48 u32 pixel_fmt; 42 u32 pixel_fmt;
49 u16 h_start_width;
50 u16 h_sync_width;
51 u16 h_end_width;
52 u16 v_start_width;
53 u16 v_sync_width;
54 u16 v_end_width;
55 u32 v_to_h_sync; 43 u32 v_to_h_sync;
56 unsigned long pixelclock; 44
57#define IPU_DI_CLKMODE_SYNC (1 << 0) 45#define IPU_DI_CLKMODE_SYNC (1 << 0)
58#define IPU_DI_CLKMODE_EXT (1 << 1) 46#define IPU_DI_CLKMODE_EXT (1 << 1)
59 unsigned long clkflags; 47 unsigned long clkflags;
@@ -236,6 +224,7 @@ void ipu_di_put(struct ipu_di *);
236int ipu_di_disable(struct ipu_di *); 224int ipu_di_disable(struct ipu_di *);
237int ipu_di_enable(struct ipu_di *); 225int ipu_di_enable(struct ipu_di *);
238int ipu_di_get_num(struct ipu_di *); 226int ipu_di_get_num(struct ipu_di *);
227int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
239int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig); 228int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
240 229
241/* 230/*