PCI: Fix whitespace, capitalization, and spelling errors

Fix whitespace, capitalization, and spelling errors.  No functional change.
I know "busses" is not an error, but "buses" was more common, so I used it
consistently.

Signed-off-by: Marta Rybczynska <rybczynska@gmail.com> (pci_reset_bridge_secondary_bus())
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

5 files changed, 71 insertions, 73 deletions

diff --git a/include/linux/msi.h b/include/linux/msi.h
index 87cce50bd121..009b02481436 100644
--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -26,11 +26,11 @@ struct msi_desc {
         struct {
                 __u8    is_msix : 1;
                 __u8    multiple: 3;    /* log2 number of messages */
-                __u8    maskbit : 1;    /* mask-pending bit supported ?   */
-                __u8    is_64   : 1;    /* Address size: 0=32bit 1=64bit  */
-                __u8    pos;            /* Location of the msi capability */
-                __u16   entry_nr;       /* specific enabled entry         */
-                unsigned default_irq;   /* default pre-assigned irq       */
+                __u8    maskbit : 1;    /* mask-pending bit supported ? */
+                __u8    is_64   : 1;    /* Address size: 0=32bit 1=64bit */
+                __u8    pos;            /* Location of the msi capability */
+                __u16   entry_nr;       /* specific enabled entry */
+                unsigned default_irq;   /* default pre-assigned irq */
         } msi_attrib;
 
         u32 masked;                     /* mask bits */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 835ec7bf6c05..1084a15175e0 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -32,7 +32,6 @@
 #include <linux/irqreturn.h>
 #include <uapi/linux/pci.h>
 
-/* Include the ID list */
 #include <linux/pci_ids.h>
 
 /*
@@ -42,9 +41,10 @@
  *
  *      7:3 = slot
  *      2:0 = function
- * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined uapi/linux/pci.h
+ *
+ * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
  * In the interest of not exposing interfaces to user-space unnecessarily,
- * the following kernel only defines are being added here.
+ * the following kernel-only defines are being added here.
  */
 #define PCI_DEVID(bus, devfn)  ((((u16)bus) << 8) | devfn)
 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
@@ -153,10 +153,10 @@ enum pcie_reset_state {
         /* Reset is NOT asserted (Use to deassert reset) */
         pcie_deassert_reset = (__force pcie_reset_state_t) 1,
 
-        /* Use #PERST to reset PCI-E device */
+        /* Use #PERST to reset PCIe device */
         pcie_warm_reset = (__force pcie_reset_state_t) 2,
 
-        /* Use PCI-E Hot Reset to reset device */
+        /* Use PCIe Hot Reset to reset device */
         pcie_hot_reset = (__force pcie_reset_state_t) 3
 };
 
@@ -259,13 +259,13 @@ struct pci_dev {
         unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
         u8              revision;       /* PCI revision, low byte of class word */
         u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
-        u8              pcie_cap;       /* PCI-E capability offset */
+        u8              pcie_cap;       /* PCIe capability offset */
         u8              msi_cap;        /* MSI capability offset */
         u8              msix_cap;       /* MSI-X capability offset */
-        u8              pcie_mpss:3;    /* PCI-E Max Payload Size Supported */
+        u8              pcie_mpss:3;    /* PCIe Max Payload Size Supported */
         u8              rom_base_reg;   /* which config register controls the ROM */
-        u8              pin;            /* which interrupt pin this device uses */
-        u16             pcie_flags_reg; /* cached PCI-E Capabilities Register */
+        u8              pin;            /* which interrupt pin this device uses */
+        u16             pcie_flags_reg; /* cached PCIe Capabilities Register */
 
         struct pci_driver *driver;      /* which driver has allocated this device */
         u64             dma_mask;       /* Mask of the bits of bus address this
@@ -300,7 +300,7 @@ struct pci_dev {
         unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
 
 #ifdef CONFIG_PCIEASPM
-        struct pcie_link_state  *link_state;    /* ASPM link state. */
+        struct pcie_link_state  *link_state;    /* ASPM link state */
 #endif
 
         pci_channel_state_t error_state;        /* current connectivity state */
@@ -317,7 +317,7 @@ struct pci_dev {
 
         bool match_driver;              /* Skip attaching driver */
         /* These fields are used by common fixups */
-        unsigned int    transparent:1;  /* Transparent PCI bridge */
+        unsigned int    transparent:1;  /* Subtractive decode PCI bridge */
         unsigned int    multifunction:1;/* Part of multi-function device */
         /* keep track of device state */
         unsigned int    is_added:1;
@@ -326,7 +326,7 @@ struct pci_dev {
         unsigned int    block_cfg_access:1;     /* config space access is blocked */
         unsigned int    broken_parity_status:1; /* Device generates false positive parity */
         unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
-        unsigned int    msi_enabled:1;
+        unsigned int    msi_enabled:1;
         unsigned int    msix_enabled:1;
         unsigned int    ari_enabled:1;  /* ARI forwarding */
         unsigned int    is_managed:1;
@@ -371,7 +371,6 @@ static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
         if (dev->is_virtfn)
                 dev = dev->physfn;
 #endif
-
         return dev;
 }
 
@@ -456,7 +455,7 @@ struct pci_bus {
         char            name[48];
 
         unsigned short  bridge_ctl;     /* manage NO_ISA/FBB/et al behaviors */
-        pci_bus_flags_t bus_flags;      /* Inherited by child busses */
+        pci_bus_flags_t bus_flags;      /* inherited by child buses */
         struct device           *bridge;
         struct device           dev;
         struct bin_attribute    *legacy_io; /* legacy I/O for this bus */
@@ -468,7 +467,7 @@ struct pci_bus {
 #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
 
 /*
- * Returns true if the pci bus is root (behind host-pci bridge),
+ * Returns true if the PCI bus is root (behind host-PCI bridge),
  * false otherwise
  *
  * Some code assumes that "bus->self == NULL" means that bus is a root bus.
@@ -510,7 +509,7 @@ static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false;
 #define PCIBIOS_BUFFER_TOO_SMALL        0x89
 
 /*
- * Translate above to generic errno for passing back through non-pci.
+ * Translate above to generic errno for passing back through non-PCI code.
  */
 static inline int pcibios_err_to_errno(int err)
 {
@@ -561,11 +560,12 @@ struct pci_dynids {
         struct list_head list;      /* for IDs added at runtime */
 };
 
-/* ---------------------------------------------------------------- */
-/** PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
- *  a set of callbacks in struct pci_error_handlers, then that device driver
- *  will be notified of PCI bus errors, and will be driven to recovery
- *  when an error occurs.
+
+/*
+ * PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
+ * a set of callbacks in struct pci_error_handlers, that device driver
+ * will be notified of PCI bus errors, and will be driven to recovery
+ * when an error occurs.
  */
 
 typedef unsigned int __bitwise pci_ers_result_t;
@@ -609,7 +609,6 @@ struct pci_error_handlers {
         void (*resume)(struct pci_dev *dev);
 };
 
-/* ---------------------------------------------------------------- */
 
 struct module;
 struct pci_driver {
@@ -713,10 +712,10 @@ extern enum pcie_bus_config_types pcie_bus_config;
 
 extern struct bus_type pci_bus_type;
 
-/* Do NOT directly access these two variables, unless you are arch specific pci
- * code, or pci core code. */
+/* Do NOT directly access these two variables, unless you are arch-specific PCI
+ * code, or PCI core code. */
 extern struct list_head pci_root_buses; /* list of all known PCI buses */
-/* Some device drivers need know if pci is initiated */
+/* Some device drivers need know if PCI is initiated */
 int no_pci_devices(void);
 
 void pcibios_resource_survey_bus(struct pci_bus *bus);
@@ -724,7 +723,7 @@ void pcibios_add_bus(struct pci_bus *bus);
 void pcibios_remove_bus(struct pci_bus *bus);
 void pcibios_fixup_bus(struct pci_bus *);
 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
-/* Architecture specific versions may override this (weak) */
+/* Architecture-specific versions may override this (weak) */
 char *pcibios_setup(char *str);
 
 /* Used only when drivers/pci/setup.c is used */
@@ -1258,7 +1257,7 @@ void pci_cfg_access_unlock(struct pci_dev *dev);
 
 /*
  * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
- * a PCI domain is defined to be a set of PCI busses which share
+ * a PCI domain is defined to be a set of PCI buses which share
  * configuration space.
  */
 #ifdef CONFIG_PCI_DOMAINS
@@ -1672,7 +1671,7 @@ extern u8 pci_cache_line_size;
 extern unsigned long pci_hotplug_io_size;
 extern unsigned long pci_hotplug_mem_size;
 
-/* Architecture specific versions may override these (weak) */
+/* Architecture-specific versions may override these (weak) */
 int pcibios_add_platform_entries(struct pci_dev *dev);
 void pcibios_disable_device(struct pci_dev *dev);
 void pcibios_set_master(struct pci_dev *dev);
diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h
index 430dd963707b..a2e2f1d17e16 100644
--- a/include/linux/pci_hotplug.h
+++ b/include/linux/pci_hotplug.h
@@ -39,8 +39,8 @@
  * @hardware_test: Called to run a specified hardware test on the specified
  * slot.
  * @get_power_status: Called to get the current power status of a slot.
- *      If this field is NULL, the value passed in the struct hotplug_slot_info
- *      will be used when this value is requested by a user.
+ *      If this field is NULL, the value passed in the struct hotplug_slot_info
+ *      will be used when this value is requested by a user.
  * @get_attention_status: Called to get the current attention status of a slot.
  *      If this field is NULL, the value passed in the struct hotplug_slot_info
  *      will be used when this value is requested by a user.
@@ -191,4 +191,3 @@ static inline int pci_get_hp_params(struct pci_dev *dev,
 
 void pci_configure_slot(struct pci_dev *dev);
 #endif
-
diff --git a/include/linux/pcieport_if.h b/include/linux/pcieport_if.h
index 9572669eea97..4f1089f2cc98 100644
--- a/include/linux/pcieport_if.h
+++ b/include/linux/pcieport_if.h
@@ -23,7 +23,7 @@
 #define PCIE_PORT_SERVICE_VC            (1 << PCIE_PORT_SERVICE_VC_SHIFT)
 
 struct pcie_device {
-        int             irq;        /* Service IRQ/MSI/MSI-X Vector */
+        int             irq;        /* Service IRQ/MSI/MSI-X Vector */
         struct pci_dev *port;       /* Root/Upstream/Downstream Port */
         u32             service;    /* Port service this device represents */
         void            *priv_data; /* Service Private Data */
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 0890556f779e..4a98e85438a7 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -13,10 +13,10 @@
  *      PCI to PCI Bridge Specification
  *      PCI System Design Guide
  *
- *      For hypertransport information, please consult the following manuals
- *      from http://www.hypertransport.org
+ *      For HyperTransport information, please consult the following manuals
+ *      from http://www.hypertransport.org
  *
- *      The Hypertransport I/O Link Specification
+ *      The HyperTransport I/O Link Specification
  */
 
 #ifndef LINUX_PCI_REGS_H
@@ -37,7 +37,7 @@
 #define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
 #define  PCI_COMMAND_VGA_PALETTE 0x20   /* Enable palette snooping */
 #define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
-#define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
+#define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
 #define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
 #define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
 #define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
@@ -45,7 +45,7 @@
 #define PCI_STATUS              0x06    /* 16 bits */
 #define  PCI_STATUS_INTERRUPT   0x08    /* Interrupt status */
 #define  PCI_STATUS_CAP_LIST    0x10    /* Support Capability List */
-#define  PCI_STATUS_66MHZ       0x20    /* Support 66 Mhz PCI 2.1 bus */
+#define  PCI_STATUS_66MHZ       0x20    /* Support 66 MHz PCI 2.1 bus */
 #define  PCI_STATUS_UDF         0x40    /* Support User Definable Features [obsolete] */
 #define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
 #define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
@@ -205,14 +205,14 @@
 #define  PCI_CAP_ID_CHSWP       0x06    /* CompactPCI HotSwap */
 #define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
 #define  PCI_CAP_ID_HT          0x08    /* HyperTransport */
-#define  PCI_CAP_ID_VNDR        0x09    /* Vendor specific */
+#define  PCI_CAP_ID_VNDR        0x09    /* Vendor-Specific */
 #define  PCI_CAP_ID_DBG         0x0A    /* Debug port */
 #define  PCI_CAP_ID_CCRC        0x0B    /* CompactPCI Central Resource Control */
-#define  PCI_CAP_ID_SHPC        0x0C    /* PCI Standard Hot-Plug Controller */
+#define  PCI_CAP_ID_SHPC        0x0C    /* PCI Standard Hot-Plug Controller */
 #define  PCI_CAP_ID_SSVID       0x0D    /* Bridge subsystem vendor/device ID */
 #define  PCI_CAP_ID_AGP3        0x0E    /* AGP Target PCI-PCI bridge */
 #define  PCI_CAP_ID_SECDEV      0x0F    /* Secure Device */
-#define  PCI_CAP_ID_EXP         0x10    /* PCI Express */
+#define  PCI_CAP_ID_EXP         0x10    /* PCI Express */
 #define  PCI_CAP_ID_MSIX        0x11    /* MSI-X */
 #define  PCI_CAP_ID_SATA        0x12    /* SATA Data/Index Conf. */
 #define  PCI_CAP_ID_AF          0x13    /* PCI Advanced Features */
@@ -268,8 +268,8 @@
 #define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
 #define  PCI_AGP_COMMAND_SBA    0x0200  /* Sideband addressing enabled */
 #define  PCI_AGP_COMMAND_AGP    0x0100  /* Allow processing of AGP transactions */
-#define  PCI_AGP_COMMAND_64BIT  0x0020  /* Allow processing of 64-bit addresses */
-#define  PCI_AGP_COMMAND_FW     0x0010  /* Force FW transfers */
+#define  PCI_AGP_COMMAND_64BIT  0x0020  /* Allow processing of 64-bit addresses */
+#define  PCI_AGP_COMMAND_FW     0x0010  /* Force FW transfers */
 #define  PCI_AGP_COMMAND_RATE4  0x0004  /* Use 4x rate */
 #define  PCI_AGP_COMMAND_RATE2  0x0002  /* Use 2x rate */
 #define  PCI_AGP_COMMAND_RATE1  0x0001  /* Use 1x rate */
@@ -321,7 +321,7 @@
 #define  PCI_MSIX_PBA_OFFSET    0xfffffff8 /* Offset into specified BAR */
 #define PCI_CAP_MSIX_SIZEOF     12      /* size of MSIX registers */
 
-/* MSI-X entry's format */
+/* MSI-X Table entry format */
 #define PCI_MSIX_ENTRY_SIZE             16
 #define  PCI_MSIX_ENTRY_LOWER_ADDR      0
 #define  PCI_MSIX_ENTRY_UPPER_ADDR      4
@@ -372,7 +372,7 @@
 #define  PCI_X_CMD_SPLIT_16     0x0060  /* Max 16 */
 #define  PCI_X_CMD_SPLIT_32     0x0070  /* Max 32 */
 #define  PCI_X_CMD_MAX_SPLIT    0x0070  /* Max Outstanding Split Transactions */
-#define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
+#define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
 #define PCI_X_STATUS            4       /* PCI-X capabilities */
 #define  PCI_X_STATUS_DEVFN     0x000000ff      /* A copy of devfn */
 #define  PCI_X_STATUS_BUS       0x0000ff00      /* A copy of bus nr */
@@ -407,8 +407,8 @@
 
 /* PCI Bridge Subsystem ID registers */
 
-#define PCI_SSVID_VENDOR_ID     4       /* PCI-Bridge subsystem vendor id register */
-#define PCI_SSVID_DEVICE_ID     6       /* PCI-Bridge subsystem device id register */
+#define PCI_SSVID_VENDOR_ID     4       /* PCI Bridge subsystem vendor ID */
+#define PCI_SSVID_DEVICE_ID     6       /* PCI Bridge subsystem device ID */
 
 /* PCI Express capability registers */
 
@@ -484,12 +484,12 @@
 #define  PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */
 #define  PCI_EXP_LNKCTL_HAWD    0x0200  /* Hardware Autonomous Width Disable */
 #define  PCI_EXP_LNKCTL_LBMIE   0x0400  /* Link Bandwidth Management Interrupt Enable */
-#define  PCI_EXP_LNKCTL_LABIE   0x0800  /* Lnk Autonomous Bandwidth Interrupt Enable */
+#define  PCI_EXP_LNKCTL_LABIE   0x0800  /* Link Autonomous Bandwidth Interrupt Enable */
 #define PCI_EXP_LNKSTA          18      /* Link Status */
 #define  PCI_EXP_LNKSTA_CLS     0x000f  /* Current Link Speed */
 #define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
 #define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
-#define  PCI_EXP_LNKSTA_NLW     0x03f0  /* Nogotiated Link Width */
+#define  PCI_EXP_LNKSTA_NLW     0x03f0  /* Negotiated Link Width */
 #define  PCI_EXP_LNKSTA_NLW_SHIFT 4     /* start of NLW mask in link status */
 #define  PCI_EXP_LNKSTA_LT      0x0800  /* Link Training */
 #define  PCI_EXP_LNKSTA_SLC     0x1000  /* Slot Clock Configuration */
@@ -593,7 +593,7 @@
 #define PCI_EXT_CAP_ID_MFVC     0x08    /* Multi-Function VC Capability */
 #define PCI_EXT_CAP_ID_VC9      0x09    /* same as _VC */
 #define PCI_EXT_CAP_ID_RCRB     0x0A    /* Root Complex RB? */
-#define PCI_EXT_CAP_ID_VNDR     0x0B    /* Vendor Specific */
+#define PCI_EXT_CAP_ID_VNDR     0x0B    /* Vendor-Specific */
 #define PCI_EXT_CAP_ID_CAC      0x0C    /* Config Access - obsolete */
 #define PCI_EXT_CAP_ID_ACS      0x0D    /* Access Control Services */
 #define PCI_EXT_CAP_ID_ARI      0x0E    /* Alternate Routing ID */
@@ -602,12 +602,12 @@
 #define PCI_EXT_CAP_ID_MRIOV    0x11    /* Multi Root I/O Virtualization */
 #define PCI_EXT_CAP_ID_MCAST    0x12    /* Multicast */
 #define PCI_EXT_CAP_ID_PRI      0x13    /* Page Request Interface */
-#define PCI_EXT_CAP_ID_AMD_XXX  0x14    /* reserved for AMD */
-#define PCI_EXT_CAP_ID_REBAR    0x15    /* resizable BAR */
-#define PCI_EXT_CAP_ID_DPA      0x16    /* dynamic power alloc */
-#define PCI_EXT_CAP_ID_TPH      0x17    /* TPH request */
-#define PCI_EXT_CAP_ID_LTR      0x18    /* latency tolerance reporting */
-#define PCI_EXT_CAP_ID_SECPCI   0x19    /* Secondary PCIe */
+#define PCI_EXT_CAP_ID_AMD_XXX  0x14    /* Reserved for AMD */
+#define PCI_EXT_CAP_ID_REBAR    0x15    /* Resizable BAR */
+#define PCI_EXT_CAP_ID_DPA      0x16    /* Dynamic Power Allocation */
+#define PCI_EXT_CAP_ID_TPH      0x17    /* TPH Requester */
+#define PCI_EXT_CAP_ID_LTR      0x18    /* Latency Tolerance Reporting */
+#define PCI_EXT_CAP_ID_SECPCI   0x19    /* Secondary PCIe Capability */
 #define PCI_EXT_CAP_ID_PMUX     0x1A    /* Protocol Multiplexing */
 #define PCI_EXT_CAP_ID_PASID    0x1B    /* Process Address Space ID */
 #define PCI_EXT_CAP_ID_MAX      PCI_EXT_CAP_ID_PASID
@@ -667,9 +667,9 @@
 #define PCI_ERR_ROOT_COR_RCV            0x00000001      /* ERR_COR Received */
 /* Multi ERR_COR Received */
 #define PCI_ERR_ROOT_MULTI_COR_RCV      0x00000002
-/* ERR_FATAL/NONFATAL Recevied */
+/* ERR_FATAL/NONFATAL Received */
 #define PCI_ERR_ROOT_UNCOR_RCV          0x00000004
-/* Multi ERR_FATAL/NONFATAL Recevied */
+/* Multi ERR_FATAL/NONFATAL Received */
 #define PCI_ERR_ROOT_MULTI_UNCOR_RCV    0x00000008
 #define PCI_ERR_ROOT_FIRST_FATAL        0x00000010      /* First Fatal */
 #define PCI_ERR_ROOT_NONFATAL_RCV       0x00000020      /* Non-Fatal Received */
@@ -678,7 +678,7 @@
 
 /* Virtual Channel */
 #define PCI_VC_PORT_REG1        4
-#define  PCI_VC_REG1_EVCC       0x7     /* extended vc count */
+#define  PCI_VC_REG1_EVCC       0x7     /* extended VC count */
 #define PCI_VC_PORT_REG2        8
 #define  PCI_VC_REG2_32_PHASE   0x2
 #define  PCI_VC_REG2_64_PHASE   0x4
@@ -711,7 +711,7 @@
 #define  PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff)
 
 /*
- * Hypertransport sub capability types
+ * HyperTransport sub capability types
  *
  * Unfortunately there are both 3 bit and 5 bit capability types defined
  * in the HT spec, catering for that is a little messy. You probably don't
@@ -739,8 +739,8 @@
 #define HT_CAPTYPE_DIRECT_ROUTE 0xB0    /* Direct routing configuration */
 #define HT_CAPTYPE_VCSET        0xB8    /* Virtual Channel configuration */
 #define HT_CAPTYPE_ERROR_RETRY  0xC0    /* Retry on error configuration */
-#define HT_CAPTYPE_GEN3         0xD0    /* Generation 3 hypertransport configuration */
-#define HT_CAPTYPE_PM           0xE0    /* Hypertransport powermanagement configuration */
+#define HT_CAPTYPE_GEN3         0xD0    /* Generation 3 HyperTransport configuration */
+#define HT_CAPTYPE_PM           0xE0    /* HyperTransport power management configuration */
 #define HT_CAP_SIZEOF_LONG      28      /* slave & primary */
 #define HT_CAP_SIZEOF_SHORT     24      /* host & secondary */
 
@@ -777,14 +777,14 @@
 #define PCI_PRI_ALLOC_REQ       0x0c    /* PRI max reqs allowed */
 #define PCI_EXT_CAP_PRI_SIZEOF  16
 
-/* PASID capability */
+/* Process Address Space ID */
 #define PCI_PASID_CAP           0x04    /* PASID feature register */
 #define  PCI_PASID_CAP_EXEC     0x02    /* Exec permissions Supported */
-#define  PCI_PASID_CAP_PRIV     0x04    /* Priviledge Mode Supported */
+#define  PCI_PASID_CAP_PRIV     0x04    /* Privilege Mode Supported */
 #define PCI_PASID_CTRL          0x06    /* PASID control register */
 #define  PCI_PASID_CTRL_ENABLE  0x01    /* Enable bit */
 #define  PCI_PASID_CTRL_EXEC    0x02    /* Exec permissions Enable */
-#define  PCI_PASID_CTRL_PRIV    0x04    /* Priviledge Mode Enable */
+#define  PCI_PASID_CTRL_PRIV    0x04    /* Privilege Mode Enable */
 #define PCI_EXT_CAP_PASID_SIZEOF        8
 
 /* Single Root I/O Virtualization */
@@ -839,22 +839,22 @@
 #define PCI_ACS_CTRL            0x06    /* ACS Control Register */
 #define PCI_ACS_EGRESS_CTL_V    0x08    /* ACS Egress Control Vector */
 
-#define PCI_VSEC_HDR            4       /* extended cap - vendor specific */
+#define PCI_VSEC_HDR            4       /* extended cap - vendor-specific */
 #define  PCI_VSEC_HDR_LEN_SHIFT 20      /* shift for length field */
 
-/* sata capability */
+/* SATA capability */
 #define PCI_SATA_REGS           4       /* SATA REGs specifier */
 #define  PCI_SATA_REGS_MASK     0xF     /* location - BAR#/inline */
 #define  PCI_SATA_REGS_INLINE   0xF     /* REGS in config space */
 #define PCI_SATA_SIZEOF_SHORT   8
 #define PCI_SATA_SIZEOF_LONG    16
 
-/* resizable BARs */
+/* Resizable BARs */
 #define PCI_REBAR_CTRL          8       /* control register */
 #define  PCI_REBAR_CTRL_NBAR_MASK       (7 << 5)        /* mask for # bars */
 #define  PCI_REBAR_CTRL_NBAR_SHIFT      5       /* shift for # bars */
 
-/* dynamic power allocation */
+/* Dynamic Power Allocation */
 #define PCI_DPA_CAP             4       /* capability register */
 #define  PCI_DPA_CAP_SUBSTATE_MASK      0x1F    /* # substates - 1 */
 #define PCI_DPA_BASE_SIZEOF     16      /* size with 0 substates */