PCI: Fix whitespace, capitalization, and spelling errors

Fix whitespace, capitalization, and spelling errors.  No functional change.
I know "busses" is not an error, but "buses" was more common, so I used it
consistently.

Signed-off-by: Marta Rybczynska <rybczynska@gmail.com> (pci_reset_bridge_secondary_bus())
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

5 files changed, 71 insertions, 73 deletions

diff --git a/include/linux/msi.h b/include/linux/msi.h
index 87cce50bd121..009b02481436 100644
--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -26,11 +26,11 @@ struct msi_desc {
         struct {
                 __u8    is_msix : 1;
                 __u8    multiple: 3;    /* log2 number of messages */
-                __u8    maskbit : 1;    /* mask-pending bit supported ?   */
-                __u8    is_64   : 1;    /* Address size: 0=32bit 1=64bit  */
-                __u8    pos;            /* Location of the msi capability */
-                __u16   entry_nr;       /* specific enabled entry         */
-                unsigned default_irq;   /* default pre-assigned irq       */
+                __u8    maskbit : 1;    /* mask-pending bit supported ? */
+                __u8    is_64   : 1;    /* Address size: 0=32bit 1=64bit */
+                __u8    pos;            /* Location of the msi capability */
+                __u16   entry_nr;       /* specific enabled entry */
+                unsigned default_irq;   /* default pre-assigned irq */
         } msi_attrib;
 
         u32 masked;                     /* mask bits */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 835ec7bf6c05..1084a15175e0 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -32,7 +32,6 @@
 #include <linux/irqreturn.h>
 #include <uapi/linux/pci.h>
 
-/* Include the ID list */
 #include <linux/pci_ids.h>
 
 /*
@@ -42,9 +41,10 @@
  *
  *      7:3 = slot
  *      2:0 = function
- * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined uapi/linux/pci.h
+ *
+ * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
  * In the interest of not exposing interfaces to user-space unnecessarily,
- * the following kernel only defines are being added here.
+ * the following kernel-only defines are being added here.
  */
 #define PCI_DEVID(bus, devfn)  ((((u16)bus) << 8) | devfn)
 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
@@ -153,10 +153,10 @@ enum pcie_reset_state {
         /* Reset is NOT asserted (Use to deassert reset) */
         pcie_deassert_reset = (__force pcie_reset_state_t) 1,
 
-        /* Use #PERST to reset PCI-E device */
+        /* Use #PERST to reset PCIe device */
         pcie_warm_reset = (__force pcie_reset_state_t) 2,
 
-        /* Use PCI-E Hot Reset to reset device */
+        /* Use PCIe Hot Reset to reset device */
         pcie_hot_reset = (__force pcie_reset_state_t) 3
 };
 
@@ -259,13 +259,13 @@ struct pci_dev {
         unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
         u8              revision;       /* PCI revision, low byte of class word */
         u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
-        u8              pcie_cap;       /* PCI-E capability offset */
+        u8              pcie_cap;       /* PCIe capability offset */
         u8              msi_cap;        /* MSI capability offset */
         u8              msix_cap;       /* MSI-X capability offset */
-        u8              pcie_mpss:3;    /* PCI-E Max Payload Size Supported */
+        u8              pcie_mpss:3;    /* PCIe Max Payload Size Supported */
         u8              rom_base_reg;   /* which config register controls the ROM */
-        u8              pin;            /* which interrupt pin this device uses */
-        u16             pcie_flags_reg; /* cached PCI-E Capabilities Register */
+        u8              pin;            /* which interrupt pin this device uses */
+        u16             pcie_flags_reg; /* cached PCIe Capabilities Register */
 
         struct pci_driver *driver;      /* which driver has allocated this device */
         u64             dma_mask;       /* Mask of the bits of bus address this
@@ -300,7 +300,7 @@ struct pci_dev {
         unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
 
 #ifdef CONFIG_PCIEASPM
-        struct pcie_link_state  *link_state;    /* ASPM link state. */
+        struct pcie_link_state  *link_state;    /* ASPM link state */
 #endif
 
         pci_channel_state_t error_state;        /* current connectivity state */
@@ -317,7 +317,7 @@ struct pci_dev {
 
         bool match_driver;              /* Skip attaching driver */
         /* These fields are used by common fixups */
-        unsigned int    transparent:1;  /* Transparent PCI bridge */
+        unsigned int    transparent:1;  /* Subtractive decode PCI bridge */
         unsigned int    multifunction:1;/* Part of multi-function device */
         /* keep track of device state */
         unsigned int    is_added:1;
@@ -326,7 +326,7 @@ struct pci_dev {
         unsigned int    block_cfg_access:1;     /* config space access is blocked */
         unsigned int    broken_parity_status:1; /* Device generates false positive parity */
         unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
-        unsigned int    msi_enabled:1;
+        unsigned int    msi_enabled:1;
         unsigned int    msix_enabled:1;
         unsigned int    ari_enabled:1;  /* ARI forwarding */
         unsigned int    is_managed:1;
@@ -371,7 +371,6 @@ static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
         if (dev->is_virtfn)
                 dev = dev->physfn;
 #endif
-
         return dev;
 }
 
@@ -456,7 +455,7 @@ struct pci_bus {
         char            name[48];
 
         unsigned short  bridge_ctl;     /* manage NO_ISA/FBB/et al behaviors */
-        pci_bus_flags_t bus_flags;      /* Inherited by child busses */
+        pci_bus_flags_t bus_flags;      /* inherited by child buses */
         struct device           *bridge;
         struct device           dev;
         struct bin_attribute    *legacy_io; /* legacy I/O for this bus */
@@ -468,7 +467,7 @@ struct pci_bus {
 #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
 
 /*
- * Returns true if the pci bus is root (behind host-pci bridge),
+ * Returns true if the PCI bus is root (behind host-PCI bridge),
  * false otherwise
  *
  * Some code assumes that "bus->self == NULL" means that bus is a root bus.
@@ -510,7 +509,7 @@ static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false;
 #define PCIBIOS_BUFFER_TOO_SMALL        0x89
 
 /*
- * Translate above to generic errno for passing back through non-pci.
+ * Translate above to generic errno for passing back through non-PCI code.
  */
 static inline int pcibios_err_to_errno(int err)
 {
@@ -561,11 +560,12 @@ struct pci_dynids {
         struct list_head list;      /* for IDs added at runtime */
 };
 
-/* ---------------------------------------------------------------- */
-/** PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
- *  a set of callbacks in struct pci_error_handlers, then that device driver
- *  will be notified of PCI bus errors, and will be driven to recovery
- *  when an error occurs.
+
+/*
+ * PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
+ * a set of callbacks in struct pci_error_handlers, that device driver
+ * will be notified of PCI bus errors, and will be driven to recovery
+ * when an error occurs.
  */
 
 typedef unsigned int __bitwise pci_ers_result_t;
@@ -609,7 +609,6 @@ struct pci_error_handlers {
         void (*resume)(struct pci_dev *dev);