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authorLinus Torvalds <torvalds@linux-foundation.org>2015-04-14 20:29:55 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-04-14 20:29:55 -0400
commitf0c1bc95a108b36677dde6c9d96a5bb810a05b75 (patch)
tree335c33469407d0ebda5670dabb49c6ecad64263e /include
parent1dcf58d6e6e6eb7ec10e9abc56887b040205b06f (diff)
parente554a99ee8d09132e80dc467433c9a4df9054645 (diff)
Merge tag 'mfd-for-linus-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones: "Changes to existing drivers: - Rename child driver [axp288_battery => axp288_fuel_gauge]; axp20x - Rename child driver [max77693-flash => max77693-led]; max77693 - Error handling fixes; intel_soc_pmic - GPIO tweaking; intel_soc_pmic - Remove non-DT code; vexpress-sysreg, tc3589x - Remove unused/legacy code; ti_am335x_tscadc, rts5249, rtsx_gops, rtsx_pcr, rtc-s5m, sec-core, max77693, menelaus, wm5102-tables - Trivial fixups; rtsx_pci, da9150-core, sec-core, max7769, max77693, mc13xxx-core, dln2, hi6421-pmic-core, rk808, twl4030-power, lpc_ich, menelaus, twl6040 - Update register/address values; rts5227, rts5249 - DT and/or binding document fixups; arizona, da9150, mt6397, axp20x, qcom-rpm, qcom-spmi-pmic - Couple of trivial core Kconfig fixups - Remove use of seq_printf return value; ab8500-debugfs - Remove __exit markups; menelaus, tps65010 - Fix platform-device name collisions; mfd-core New drivers/supported devices: - Add support for wm8280/wm8281 into arizona - Add support for COMe-cBL6 into kempld-core - Add support for rts524a and rts525a into rts5249 - Add support for ipq8064 into qcom_rpm - Add support for extcon into axp20x - New MediaTek MT6397 PMIC driver - New Maxim MAX77843 PMIC dirver - New Intel Quark X1000 I2C-GPIO driver - New Skyworks SKY81452 driver" * tag 'mfd-for-linus-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (76 commits) mfd: sec: Fix RTC alarm interrupt number on S2MPS11 mfd: wm5102: Remove registers for output 3R from readable list mfd: tps65010: Remove incorrect __exit markups mfd: devicetree: bindings: Add Qualcomm RPM regulator subnodes mfd: axp20x: Add support for extcon cell mfd: lpc_ich: Sort IDs mfd: twl6040: Remove wrong and unneeded "platform:twl6040" modalias mfd: qcom-spmi-pmic: Add specific compatible strings for Qualcomm's SPMI PMIC's mfd: axp20x: Fix duplicate const for model names mfd: menelaus: Use macro for magic number mfd: menelaus: Drop support for SW controller VCORE mfd: menelaus: Delete omap_has_menelaus mfd: arizona: Correct type of gpio_defaults mfd: lpc_ich: Sort IDs mfd: Fix a typo in Kconfig mfd: qcom_rpm: Add support for IPQ8064 mfd: devicetree: qcom_rpm: Document IPQ8064 resources mfd: core: Fix platform-device name collisions mfd: intel_quark_i2c_gpio: Don't crash if !DMI dt-bindings: Add vendor-prefix for X-Powers ...
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/mfd/arizona.h (renamed from include/linux/mfd/arizona/gpio.h)67
-rw-r--r--include/dt-bindings/mfd/qcom-rpm.h6
-rw-r--r--include/linux/mfd/arizona/core.h1
-rw-r--r--include/linux/mfd/arizona/pdata.h24
-rw-r--r--include/linux/mfd/max77693-private.h5
-rw-r--r--include/linux/mfd/max77693.h13
-rw-r--r--include/linux/mfd/max77843-private.h454
-rw-r--r--include/linux/mfd/menelaus.h7
-rw-r--r--include/linux/mfd/mt6397/core.h64
-rw-r--r--include/linux/mfd/mt6397/registers.h362
-rw-r--r--include/linux/mfd/rk808.h3
-rw-r--r--include/linux/mfd/rtsx_pci.h1116
-rw-r--r--include/linux/mfd/samsung/core.h9
-rw-r--r--include/linux/mfd/samsung/irq.h2
-rw-r--r--include/linux/mfd/sky81452.h31
-rw-r--r--include/linux/mfd/ti_am335x_tscadc.h1
-rw-r--r--include/linux/platform_data/sky81452-backlight.h46
17 files changed, 1584 insertions, 627 deletions
diff --git a/include/linux/mfd/arizona/gpio.h b/include/dt-bindings/mfd/arizona.h
index d2146bb74f89..c7af7c7ef793 100644
--- a/include/linux/mfd/arizona/gpio.h
+++ b/include/dt-bindings/mfd/arizona.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GPIO configuration for Arizona devices 2 * Device Tree defines for Arizona devices
3 * 3 *
4 * Copyright 2013 Wolfson Microelectronics. PLC. 4 * Copyright 2015 Cirrus Logic Inc.
5 * 5 *
6 * Author: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> 6 * Author: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
7 * 7 *
@@ -10,9 +10,10 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13#ifndef _ARIZONA_GPIO_H 13#ifndef _DT_BINDINGS_MFD_ARIZONA_H
14#define _ARIZONA_GPIO_H 14#define _DT_BINDINGS_MFD_ARIZONA_H
15 15
16/* GPIO Function Definitions */
16#define ARIZONA_GP_FN_TXLRCLK 0x00 17#define ARIZONA_GP_FN_TXLRCLK 0x00
17#define ARIZONA_GP_FN_GPIO 0x01 18#define ARIZONA_GP_FN_GPIO 0x01
18#define ARIZONA_GP_FN_IRQ1 0x02 19#define ARIZONA_GP_FN_IRQ1 0x02
@@ -61,36 +62,32 @@
61#define ARIZONA_GP_FN_SYSCLK_ENA_STATUS 0x4B 62#define ARIZONA_GP_FN_SYSCLK_ENA_STATUS 0x4B
62#define ARIZONA_GP_FN_ASYNCCLK_ENA_STATUS 0x4C 63#define ARIZONA_GP_FN_ASYNCCLK_ENA_STATUS 0x4C
63 64
64#define ARIZONA_GPN_DIR 0x8000 /* GPN_DIR */ 65/* GPIO Configuration Bits */
65#define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */ 66#define ARIZONA_GPN_DIR 0x8000
66#define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */ 67#define ARIZONA_GPN_PU 0x4000
67#define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */ 68#define ARIZONA_GPN_PD 0x2000
68#define ARIZONA_GPN_PU 0x4000 /* GPN_PU */ 69#define ARIZONA_GPN_LVL 0x0800
69#define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */ 70#define ARIZONA_GPN_POL 0x0400
70#define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */ 71#define ARIZONA_GPN_OP_CFG 0x0200
71#define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */ 72#define ARIZONA_GPN_DB 0x0100
72#define ARIZONA_GPN_PD 0x2000 /* GPN_PD */ 73
73#define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */ 74/* Provide some defines for the most common configs */
74#define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */ 75#define ARIZONA_GP_DEFAULT 0xffffffff
75#define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */ 76#define ARIZONA_GP_OUTPUT (ARIZONA_GP_FN_GPIO)
76#define ARIZONA_GPN_LVL 0x0800 /* GPN_LVL */ 77#define ARIZONA_GP_INPUT (ARIZONA_GP_FN_GPIO | \
77#define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */ 78 ARIZONA_GPN_DIR)
78#define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */ 79
79#define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */ 80#define ARIZONA_32KZ_MCLK1 1
80#define ARIZONA_GPN_POL 0x0400 /* GPN_POL */ 81#define ARIZONA_32KZ_MCLK2 2
81#define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */ 82#define ARIZONA_32KZ_NONE 3
82#define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */ 83
83#define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */ 84#define ARIZONA_DMIC_MICVDD 0
84#define ARIZONA_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */ 85#define ARIZONA_DMIC_MICBIAS1 1
85#define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */ 86#define ARIZONA_DMIC_MICBIAS2 2
86#define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */ 87#define ARIZONA_DMIC_MICBIAS3 3
87#define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */ 88
88#define ARIZONA_GPN_DB 0x0100 /* GPN_DB */ 89#define ARIZONA_INMODE_DIFF 0
89#define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */ 90#define ARIZONA_INMODE_SE 1
90#define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */ 91#define ARIZONA_INMODE_DMIC 2
91#define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */
92#define ARIZONA_GPN_FN_MASK 0x007F /* GPN_DB */
93#define ARIZONA_GPN_FN_SHIFT 0 /* GPN_DB */
94#define ARIZONA_GPN_FN_WIDTH 7 /* GPN_DB */
95 92
96#endif 93#endif
diff --git a/include/dt-bindings/mfd/qcom-rpm.h b/include/dt-bindings/mfd/qcom-rpm.h
index 388a6f3d6165..13a9d4bf2662 100644
--- a/include/dt-bindings/mfd/qcom-rpm.h
+++ b/include/dt-bindings/mfd/qcom-rpm.h
@@ -141,6 +141,12 @@
141#define QCOM_RPM_SYS_FABRIC_MODE 131 141#define QCOM_RPM_SYS_FABRIC_MODE 131
142#define QCOM_RPM_USB_OTG_SWITCH 132 142#define QCOM_RPM_USB_OTG_SWITCH 132
143#define QCOM_RPM_VDDMIN_GPIO 133 143#define QCOM_RPM_VDDMIN_GPIO 133
144#define QCOM_RPM_NSS_FABRIC_0_CLK 134
145#define QCOM_RPM_NSS_FABRIC_1_CLK 135
146#define QCOM_RPM_SMB208_S1a 136
147#define QCOM_RPM_SMB208_S1b 137
148#define QCOM_RPM_SMB208_S2a 138
149#define QCOM_RPM_SMB208_S2b 139
144 150
145/* 151/*
146 * Constants used to select force mode for regulators. 152 * Constants used to select force mode for regulators.
diff --git a/include/linux/mfd/arizona/core.h b/include/linux/mfd/arizona/core.h
index 910e3aa1e965..f97010576f56 100644
--- a/include/linux/mfd/arizona/core.h
+++ b/include/linux/mfd/arizona/core.h
@@ -24,6 +24,7 @@ enum arizona_type {
24 WM5102 = 1, 24 WM5102 = 1,
25 WM5110 = 2, 25 WM5110 = 2,
26 WM8997 = 3, 26 WM8997 = 3,
27 WM8280 = 4,
27}; 28};
28 29
29#define ARIZONA_IRQ_GP1 0 30#define ARIZONA_IRQ_GP1 0
diff --git a/include/linux/mfd/arizona/pdata.h b/include/linux/mfd/arizona/pdata.h
index 4578c72c9b86..1789cb0f4f17 100644
--- a/include/linux/mfd/arizona/pdata.h
+++ b/include/linux/mfd/arizona/pdata.h
@@ -11,31 +11,26 @@
11#ifndef _ARIZONA_PDATA_H 11#ifndef _ARIZONA_PDATA_H
12#define _ARIZONA_PDATA_H 12#define _ARIZONA_PDATA_H
13 13
14#define ARIZONA_GPN_DIR 0x8000 /* GPN_DIR */ 14#include <dt-bindings/mfd/arizona.h>
15
15#define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */ 16#define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */
16#define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */ 17#define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */
17#define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */ 18#define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */
18#define ARIZONA_GPN_PU 0x4000 /* GPN_PU */
19#define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */ 19#define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */
20#define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */ 20#define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */
21#define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */ 21#define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */
22#define ARIZONA_GPN_PD 0x2000 /* GPN_PD */
23#define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */ 22#define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */
24#define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */ 23#define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */
25#define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */ 24#define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */
26#define ARIZONA_GPN_LVL 0x0800 /* GPN_LVL */
27#define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */ 25#define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */
28#define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */ 26#define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */
29#define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */ 27#define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */
30#define ARIZONA_GPN_POL 0x0400 /* GPN_POL */
31#define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */ 28#define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */
32#define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */ 29#define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */
33#define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */ 30#define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */
34#define ARIZONA_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */
35#define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */ 31#define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
36#define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */ 32#define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */
37#define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */ 33#define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */
38#define ARIZONA_GPN_DB 0x0100 /* GPN_DB */
39#define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */ 34#define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */
40#define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */ 35#define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */
41#define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */ 36#define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */
@@ -45,23 +40,10 @@
45 40
46#define ARIZONA_MAX_GPIO 5 41#define ARIZONA_MAX_GPIO 5
47 42
48#define ARIZONA_32KZ_MCLK1 1
49#define ARIZONA_32KZ_MCLK2 2
50#define ARIZONA_32KZ_NONE 3
51
52#define ARIZONA_MAX_INPUT 4 43#define ARIZONA_MAX_INPUT 4
53 44
54#define ARIZONA_DMIC_MICVDD 0
55#define ARIZONA_DMIC_MICBIAS1 1
56#define ARIZONA_DMIC_MICBIAS2 2
57#define ARIZONA_DMIC_MICBIAS3 3
58
59#define ARIZONA_MAX_MICBIAS 3 45#define ARIZONA_MAX_MICBIAS 3
60 46
61#define ARIZONA_INMODE_DIFF 0
62#define ARIZONA_INMODE_SE 1
63#define ARIZONA_INMODE_DMIC 2
64
65#define ARIZONA_MAX_OUTPUT 6 47#define ARIZONA_MAX_OUTPUT 6
66 48
67#define ARIZONA_MAX_AIF 3 49#define ARIZONA_MAX_AIF 3
@@ -112,7 +94,7 @@ struct arizona_pdata {
112 int gpio_base; 94 int gpio_base;
113 95
114 /** Pin state for GPIO pins */ 96 /** Pin state for GPIO pins */
115 int gpio_defaults[ARIZONA_MAX_GPIO]; 97 unsigned int gpio_defaults[ARIZONA_MAX_GPIO];
116 98
117 /** 99 /**
118 * Maximum number of channels clocks will be generated for, 100 * Maximum number of channels clocks will be generated for,
diff --git a/include/linux/mfd/max77693-private.h b/include/linux/mfd/max77693-private.h
index 955dd990beaf..51633ea6f910 100644
--- a/include/linux/mfd/max77693-private.h
+++ b/include/linux/mfd/max77693-private.h
@@ -87,6 +87,7 @@ enum max77693_pmic_reg {
87/* MAX77693 ITORCH register */ 87/* MAX77693 ITORCH register */
88#define TORCH_IOUT1_SHIFT 0 88#define TORCH_IOUT1_SHIFT 0
89#define TORCH_IOUT2_SHIFT 4 89#define TORCH_IOUT2_SHIFT 4
90#define TORCH_IOUT_MASK(x) (0xf << (x))
90#define TORCH_IOUT_MIN 15625 91#define TORCH_IOUT_MIN 15625
91#define TORCH_IOUT_MAX 250000 92#define TORCH_IOUT_MAX 250000
92#define TORCH_IOUT_STEP 15625 93#define TORCH_IOUT_STEP 15625
@@ -113,8 +114,8 @@ enum max77693_pmic_reg {
113#define FLASH_EN_FLASH 0x1 114#define FLASH_EN_FLASH 0x1
114#define FLASH_EN_TORCH 0x2 115#define FLASH_EN_TORCH 0x2
115#define FLASH_EN_ON 0x3 116#define FLASH_EN_ON 0x3
116#define FLASH_EN_SHIFT(x) (6 - ((x) - 1) * 2) 117#define FLASH_EN_SHIFT(x) (6 - (x) * 2)
117#define TORCH_EN_SHIFT(x) (2 - ((x) - 1) * 2) 118#define TORCH_EN_SHIFT(x) (2 - (x) * 2)
118 119
119/* MAX77693 MAX_FLASH1 register */ 120/* MAX77693 MAX_FLASH1 register */
120#define MAX_FLASH1_MAX_FL_EN 0x80 121#define MAX_FLASH1_MAX_FL_EN 0x80
diff --git a/include/linux/mfd/max77693.h b/include/linux/mfd/max77693.h
index 09a4dedaeea8..d450f687301b 100644
--- a/include/linux/mfd/max77693.h
+++ b/include/linux/mfd/max77693.h
@@ -81,19 +81,6 @@ enum max77693_led_boost_mode {
81 MAX77693_LED_BOOST_FIXED, 81 MAX77693_LED_BOOST_FIXED,
82}; 82};
83 83
84struct max77693_led_platform_data {
85 u32 fleds[2];
86 u32 iout_torch[2];
87 u32 iout_flash[2];
88 u32 trigger[2];
89 u32 trigger_type[2];
90 u32 num_leds;
91 u32 boost_mode;
92 u32 flash_timeout;
93 u32 boost_vout;
94 u32 low_vsys;
95};
96
97/* MAX77693 */ 84/* MAX77693 */
98 85
99struct max77693_platform_data { 86struct max77693_platform_data {
diff --git a/include/linux/mfd/max77843-private.h b/include/linux/mfd/max77843-private.h
new file mode 100644
index 000000000000..7178ace8379e
--- /dev/null
+++ b/include/linux/mfd/max77843-private.h
@@ -0,0 +1,454 @@
1/*
2 * Common variables for the Maxim MAX77843 driver
3 *
4 * Copyright (C) 2015 Samsung Electronics
5 * Author: Jaewon Kim <jaewon02.kim@samsung.com>
6 * Author: Beomho Seo <beomho.seo@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef __MAX77843_PRIVATE_H_
15#define __MAX77843_PRIVATE_H_
16
17#include <linux/i2c.h>
18#include <linux/regmap.h>
19
20#define I2C_ADDR_TOPSYS (0xCC >> 1)
21#define I2C_ADDR_CHG (0xD2 >> 1)
22#define I2C_ADDR_FG (0x6C >> 1)
23#define I2C_ADDR_MUIC (0x4A >> 1)
24
25/* Topsys, Haptic and LED registers */
26enum max77843_sys_reg {
27 MAX77843_SYS_REG_PMICID = 0x00,
28 MAX77843_SYS_REG_PMICREV = 0x01,
29 MAX77843_SYS_REG_MAINCTRL1 = 0x02,
30 MAX77843_SYS_REG_INTSRC = 0x22,
31 MAX77843_SYS_REG_INTSRCMASK = 0x23,
32 MAX77843_SYS_REG_SYSINTSRC = 0x24,
33 MAX77843_SYS_REG_SYSINTMASK = 0x26,
34 MAX77843_SYS_REG_TOPSYS_STAT = 0x28,
35 MAX77843_SYS_REG_SAFEOUTCTRL = 0xC6,
36
37 MAX77843_SYS_REG_END,
38};
39
40enum max77843_haptic_reg {
41 MAX77843_HAP_REG_MCONFIG = 0x10,
42
43 MAX77843_HAP_REG_END,
44};
45
46enum max77843_led_reg {
47 MAX77843_LED_REG_LEDEN = 0x30,
48 MAX77843_LED_REG_LED0BRT = 0x31,
49 MAX77843_LED_REG_LED1BRT = 0x32,
50 MAX77843_LED_REG_LED2BRT = 0x33,
51 MAX77843_LED_REG_LED3BRT = 0x34,
52 MAX77843_LED_REG_LEDBLNK = 0x38,
53 MAX77843_LED_REG_LEDRAMP = 0x36,
54
55 MAX77843_LED_REG_END,
56};
57
58/* Charger registers */
59enum max77843_charger_reg {
60 MAX77843_CHG_REG_CHG_INT = 0xB0,
61 MAX77843_CHG_REG_CHG_INT_MASK = 0xB1,
62 MAX77843_CHG_REG_CHG_INT_OK = 0xB2,
63 MAX77843_CHG_REG_CHG_DTLS_00 = 0xB3,
64 MAX77843_CHG_REG_CHG_DTLS_01 = 0xB4,
65 MAX77843_CHG_REG_CHG_DTLS_02 = 0xB5,
66 MAX77843_CHG_REG_CHG_CNFG_00 = 0xB7,
67 MAX77843_CHG_REG_CHG_CNFG_01 = 0xB8,
68 MAX77843_CHG_REG_CHG_CNFG_02 = 0xB9,
69 MAX77843_CHG_REG_CHG_CNFG_03 = 0xBA,
70 MAX77843_CHG_REG_CHG_CNFG_04 = 0xBB,
71 MAX77843_CHG_REG_CHG_CNFG_06 = 0xBD,
72 MAX77843_CHG_REG_CHG_CNFG_07 = 0xBE,
73 MAX77843_CHG_REG_CHG_CNFG_09 = 0xC0,
74 MAX77843_CHG_REG_CHG_CNFG_10 = 0xC1,
75 MAX77843_CHG_REG_CHG_CNFG_11 = 0xC2,
76 MAX77843_CHG_REG_CHG_CNFG_12 = 0xC3,
77
78 MAX77843_CHG_REG_END,
79};
80
81/* Fuel gauge registers */
82enum max77843_fuelgauge {
83 MAX77843_FG_REG_STATUS = 0x00,
84 MAX77843_FG_REG_VALRT_TH = 0x01,
85 MAX77843_FG_REG_TALRT_TH = 0x02,
86 MAX77843_FG_REG_SALRT_TH = 0x03,
87 MAX77843_FG_RATE_AT_RATE = 0x04,
88 MAX77843_FG_REG_REMCAP_REP = 0x05,
89 MAX77843_FG_REG_SOCREP = 0x06,
90 MAX77843_FG_REG_AGE = 0x07,
91 MAX77843_FG_REG_TEMP = 0x08,
92 MAX77843_FG_REG_VCELL = 0x09,
93 MAX77843_FG_REG_CURRENT = 0x0A,
94 MAX77843_FG_REG_AVG_CURRENT = 0x0B,
95 MAX77843_FG_REG_SOCMIX = 0x0D,
96 MAX77843_FG_REG_SOCAV = 0x0E,
97 MAX77843_FG_REG_REMCAP_MIX = 0x0F,
98 MAX77843_FG_REG_FULLCAP = 0x10,
99 MAX77843_FG_REG_AVG_TEMP = 0x16,
100 MAX77843_FG_REG_CYCLES = 0x17,
101 MAX77843_FG_REG_AVG_VCELL = 0x19,
102 MAX77843_FG_REG_CONFIG = 0x1D,
103 MAX77843_FG_REG_REMCAP_AV = 0x1F,
104 MAX77843_FG_REG_FULLCAP_NOM = 0x23,
105 MAX77843_FG_REG_MISCCFG = 0x2B,
106 MAX77843_FG_REG_RCOMP = 0x38,
107 MAX77843_FG_REG_FSTAT = 0x3D,
108 MAX77843_FG_REG_DQACC = 0x45,
109 MAX77843_FG_REG_DPACC = 0x46,
110 MAX77843_FG_REG_OCV = 0xEE,
111 MAX77843_FG_REG_VFOCV = 0xFB,
112 MAX77843_FG_SOCVF = 0xFF,
113
114 MAX77843_FG_END,
115};
116
117/* MUIC registers */
118enum max77843_muic_reg {
119 MAX77843_MUIC_REG_ID = 0x00,
120 MAX77843_MUIC_REG_INT1 = 0x01,
121 MAX77843_MUIC_REG_INT2 = 0x02,
122 MAX77843_MUIC_REG_INT3 = 0x03,
123 MAX77843_MUIC_REG_STATUS1 = 0x04,
124 MAX77843_MUIC_REG_STATUS2 = 0x05,
125 MAX77843_MUIC_REG_STATUS3 = 0x06,
126 MAX77843_MUIC_REG_INTMASK1 = 0x07,
127 MAX77843_MUIC_REG_INTMASK2 = 0x08,
128 MAX77843_MUIC_REG_INTMASK3 = 0x09,
129 MAX77843_MUIC_REG_CDETCTRL1 = 0x0A,
130 MAX77843_MUIC_REG_CDETCTRL2 = 0x0B,
131 MAX77843_MUIC_REG_CONTROL1 = 0x0C,
132 MAX77843_MUIC_REG_CONTROL2 = 0x0D,
133 MAX77843_MUIC_REG_CONTROL3 = 0x0E,
134 MAX77843_MUIC_REG_CONTROL4 = 0x16,
135 MAX77843_MUIC_REG_HVCONTROL1 = 0x17,
136 MAX77843_MUIC_REG_HVCONTROL2 = 0x18,
137
138 MAX77843_MUIC_REG_END,
139};
140
141enum max77843_irq {
142 /* Topsys: SYSTEM */
143 MAX77843_SYS_IRQ_SYSINTSRC_SYSUVLO_INT,
144 MAX77843_SYS_IRQ_SYSINTSRC_SYSOVLO_INT,
145 MAX77843_SYS_IRQ_SYSINTSRC_TSHDN_INT,
146 MAX77843_SYS_IRQ_SYSINTSRC_TM_INT,
147
148 /* Charger: CHG_INT */
149 MAX77843_CHG_IRQ_CHG_INT_BYP_I,
150 MAX77843_CHG_IRQ_CHG_INT_BATP_I,
151 MAX77843_CHG_IRQ_CHG_INT_BAT_I,
152 MAX77843_CHG_IRQ_CHG_INT_CHG_I,
153 MAX77843_CHG_IRQ_CHG_INT_WCIN_I,
154 MAX77843_CHG_IRQ_CHG_INT_CHGIN_I,
155 MAX77843_CHG_IRQ_CHG_INT_AICL_I,
156
157 MAX77843_IRQ_NUM,
158};
159
160enum max77843_irq_muic {
161 /* MUIC: INT1 */
162 MAX77843_MUIC_IRQ_INT1_ADC,
163 MAX77843_MUIC_IRQ_INT1_ADCERROR,
164 MAX77843_MUIC_IRQ_INT1_ADC1K,
165
166 /* MUIC: INT2 */
167 MAX77843_MUIC_IRQ_INT2_CHGTYP,
168 MAX77843_MUIC_IRQ_INT2_CHGDETRUN,
169 MAX77843_MUIC_IRQ_INT2_DCDTMR,
170 MAX77843_MUIC_IRQ_INT2_DXOVP,
171 MAX77843_MUIC_IRQ_INT2_VBVOLT,
172
173 /* MUIC: INT3 */
174 MAX77843_MUIC_IRQ_INT3_VBADC,
175 MAX77843_MUIC_IRQ_INT3_VDNMON,
176 MAX77843_MUIC_IRQ_INT3_DNRES,
177 MAX77843_MUIC_IRQ_INT3_MPNACK,
178 MAX77843_MUIC_IRQ_INT3_MRXBUFOW,
179 MAX77843_MUIC_IRQ_INT3_MRXTRF,
180 MAX77843_MUIC_IRQ_INT3_MRXPERR,
181 MAX77843_MUIC_IRQ_INT3_MRXRDY,
182
183 MAX77843_MUIC_IRQ_NUM,
184};
185
186/* MAX77843 interrupts */
187#define MAX77843_SYS_IRQ_SYSUVLO_INT BIT(0)
188#define MAX77843_SYS_IRQ_SYSOVLO_INT BIT(1)
189#define MAX77843_SYS_IRQ_TSHDN_INT BIT(2)
190#define MAX77843_SYS_IRQ_TM_INT BIT(3)
191
192/* MAX77843 MAINCTRL1 register */
193#define MAINCTRL1_BIASEN_SHIFT 7
194#define MAX77843_MAINCTRL1_BIASEN_MASK BIT(MAINCTRL1_BIASEN_SHIFT)
195
196/* MAX77843 MCONFIG register */
197#define MCONFIG_MODE_SHIFT 7
198#define MCONFIG_MEN_SHIFT 6
199#define MCONFIG_PDIV_SHIFT 0
200
201#define MAX77843_MCONFIG_MODE_MASK BIT(MCONFIG_MODE_SHIFT)
202#define MAX77843_MCONFIG_MEN_MASK BIT(MCONFIG_MEN_SHIFT)
203#define MAX77843_MCONFIG_PDIV_MASK (0x3 << MCONFIG_PDIV_SHIFT)
204
205/* Max77843 charger insterrupts */
206#define MAX77843_CHG_BYP_I BIT(0)
207#define MAX77843_CHG_BATP_I BIT(2)
208#define MAX77843_CHG_BAT_I BIT(3)
209#define MAX77843_CHG_CHG_I BIT(4)
210#define MAX77843_CHG_WCIN_I BIT(5)
211#define MAX77843_CHG_CHGIN_I BIT(6)
212#define MAX77843_CHG_AICL_I BIT(7)
213
214/* MAX77843 CHG_INT_OK register */
215#define MAX77843_CHG_BYP_OK BIT(0)
216#define MAX77843_CHG_BATP_OK BIT(2)
217#define MAX77843_CHG_BAT_OK BIT(3)
218#define MAX77843_CHG_CHG_OK BIT(4)
219#define MAX77843_CHG_WCIN_OK BIT(5)
220#define MAX77843_CHG_CHGIN_OK BIT(6)
221#define MAX77843_CHG_AICL_OK BIT(7)
222
223/* MAX77843 CHG_DETAILS_00 register */
224#define MAX77843_CHG_BAT_DTLS BIT(0)
225
226/* MAX77843 CHG_DETAILS_01 register */
227#define MAX77843_CHG_DTLS_MASK 0x0f
228#define MAX77843_CHG_PQ_MODE 0x00
229#define MAX77843_CHG_CC_MODE 0x01
230#define MAX77843_CHG_CV_MODE 0x02
231#define MAX77843_CHG_TO_MODE 0x03
232#define MAX77843_CHG_DO_MODE 0x04
233#define MAX77843_CHG_HT_MODE 0x05
234#define MAX77843_CHG_TF_MODE 0x06
235#define MAX77843_CHG_TS_MODE 0x07
236#define MAX77843_CHG_OFF_MODE 0x08
237
238#define MAX77843_CHG_BAT_DTLS_MASK 0xf0
239#define MAX77843_CHG_NO_BAT (0x00 << 4)
240#define MAX77843_CHG_LOW_VOLT_BAT (0x01 << 4)
241#define MAX77843_CHG_LONG_BAT_TIME (0x02 << 4)
242#define MAX77843_CHG_OK_BAT (0x03 << 4)
243#define MAX77843_CHG_OK_LOW_VOLT_BAT (0x04 << 4)
244#define MAX77843_CHG_OVER_VOLT_BAT (0x05 << 4)
245#define MAX77843_CHG_OVER_CURRENT_BAT (0x06 << 4)
246
247/* MAX77843 CHG_CNFG_00 register */
248#define MAX77843_CHG_DISABLE 0x00
249#define MAX77843_CHG_ENABLE 0x05
250#define MAX77843_CHG_MASK 0x01
251#define MAX77843_CHG_BUCK_MASK 0x04
252
253/* MAX77843 CHG_CNFG_01 register */
254#define MAX77843_CHG_RESTART_THRESHOLD_100 0x00
255#define MAX77843_CHG_RESTART_THRESHOLD_150 0x10
256#define MAX77843_CHG_RESTART_THRESHOLD_200 0x20
257#define MAX77843_CHG_RESTART_THRESHOLD_DISABLE 0x30
258
259/* MAX77843 CHG_CNFG_02 register */
260#define MAX77843_CHG_FAST_CHG_CURRENT_MIN 100000
261#define MAX77843_CHG_FAST_CHG_CURRENT_MAX 3150000
262#define MAX77843_CHG_FAST_CHG_CURRENT_STEP 50000
263#define MAX77843_CHG_FAST_CHG_CURRENT_MASK 0x3f
264#define MAX77843_CHG_OTG_ILIMIT_500 (0x00 << 6)
265#define MAX77843_CHG_OTG_ILIMIT_900 (0x01 << 6)
266#define MAX77843_CHG_OTG_ILIMIT_1200 (0x02 << 6)
267#define MAX77843_CHG_OTG_ILIMIT_1500 (0x03 << 6)
268#define MAX77843_CHG_OTG_ILIMIT_MASK 0xc0
269
270/* MAX77843 CHG_CNFG_03 register */
271#define MAX77843_CHG_TOP_OFF_CURRENT_MIN 125000
272#define MAX77843_CHG_TOP_OFF_CURRENT_MAX 650000
273#define MAX77843_CHG_TOP_OFF_CURRENT_STEP 75000
274#define MAX77843_CHG_TOP_OFF_CURRENT_MASK 0x07
275
276/* MAX77843 CHG_CNFG_06 register */
277#define MAX77843_CHG_WRITE_CAP_BLOCK 0x10
278#define MAX77843_CHG_WRITE_CAP_UNBLOCK 0x0C
279
280/* MAX77843_CHG_CNFG_09_register */
281#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MIN 100000
282#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MAX 4000000
283#define MAX77843_CHG_INPUT_CURRENT_LIMIT_REF 3367000
284#define MAX77843_CHG_INPUT_CURRENT_LIMIT_STEP 33000
285
286#define MAX77843_MUIC_ADC BIT(0)
287#define MAX77843_MUIC_ADCERROR BIT(2)
288#define MAX77843_MUIC_ADC1K BIT(3)
289
290#define MAX77843_MUIC_CHGTYP BIT(0)
291#define MAX77843_MUIC_CHGDETRUN BIT(1)
292#define MAX77843_MUIC_DCDTMR BIT(2)
293#define MAX77843_MUIC_DXOVP BIT(3)
294#define MAX77843_MUIC_VBVOLT BIT(4)
295
296#define MAX77843_MUIC_VBADC BIT(0)
297#define MAX77843_MUIC_VDNMON BIT(1)
298#define MAX77843_MUIC_DNRES BIT(2)
299#define MAX77843_MUIC_MPNACK BIT(3)
300#define MAX77843_MUIC_MRXBUFOW BIT(4)
301#define MAX77843_MUIC_MRXTRF BIT(5)
302#define MAX77843_MUIC_MRXPERR BIT(6)
303#define MAX77843_MUIC_MRXRDY BIT(7)
304
305/* MAX77843 INTSRCMASK register */
306#define MAX77843_INTSRCMASK_CHGR 0
307#define MAX77843_INTSRCMASK_SYS 1
308#define MAX77843_INTSRCMASK_FG 2
309#define MAX77843_INTSRCMASK_MUIC 3
310
311#define MAX77843_INTSRCMASK_CHGR_MASK BIT(MAX77843_INTSRCMASK_CHGR)
312#define MAX77843_INTSRCMASK_SYS_MASK BIT(MAX77843_INTSRCMASK_SYS)
313#define MAX77843_INTSRCMASK_FG_MASK BIT(MAX77843_INTSRCMASK_FG)
314#define MAX77843_INTSRCMASK_MUIC_MASK BIT(MAX77843_INTSRCMASK_MUIC)
315
316#define MAX77843_INTSRC_MASK_MASK \
317 (MAX77843_INTSRCMASK_MUIC_MASK | MAX77843_INTSRCMASK_FG_MASK | \
318 MAX77843_INTSRCMASK_SYS_MASK | MAX77843_INTSRCMASK_CHGR_MASK)
319
320/* MAX77843 STATUS register*/
321#define STATUS1_ADC_SHIFT 0
322#define STATUS1_ADCERROR_SHIFT 6
323#define STATUS1_ADC1K_SHIFT 7
324#define STATUS2_CHGTYP_SHIFT 0
325#define STATUS2_CHGDETRUN_SHIFT 3
326#define STATUS2_DCDTMR_SHIFT 4
327#define STATUS2_DXOVP_SHIFT 5
328#define STATUS2_VBVOLT_SHIFT 6
329#define STATUS3_VBADC_SHIFT 0
330#define STATUS3_VDNMON_SHIFT 4
331#define STATUS3_DNRES_SHIFT 5
332#define STATUS3_MPNACK_SHIFT 6
333
334#define MAX77843_MUIC_STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
335#define MAX77843_MUIC_STATUS1_ADCERROR_MASK BIT(STATUS1_ADCERROR_SHIFT)
336#define MAX77843_MUIC_STATUS1_ADC1K_MASK BIT(STATUS1_ADC1K_SHIFT)
337#define MAX77843_MUIC_STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
338#define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK BIT(STATUS2_CHGDETRUN_SHIFT)
339#define MAX77843_MUIC_STATUS2_DCDTMR_MASK BIT(STATUS2_DCDTMR_SHIFT)
340#define MAX77843_MUIC_STATUS2_DXOVP_MASK BIT(STATUS2_DXOVP_SHIFT)
341#define MAX77843_MUIC_STATUS2_VBVOLT_MASK BIT(STATUS2_VBVOLT_SHIFT)
342#define MAX77843_MUIC_STATUS3_VBADC_MASK (0xf << STATUS3_VBADC_SHIFT)
343#define MAX77843_MUIC_STATUS3_VDNMON_MASK BIT(STATUS3_VDNMON_SHIFT)
344#define MAX77843_MUIC_STATUS3_DNRES_MASK BIT(STATUS3_DNRES_SHIFT)
345#define MAX77843_MUIC_STATUS3_MPNACK_MASK BIT(STATUS3_MPNACK_SHIFT)
346
347/* MAX77843 CONTROL register */
348#define CONTROL1_COMP1SW_SHIFT 0
349#define CONTROL1_COMP2SW_SHIFT 3
350#define CONTROL1_IDBEN_SHIFT 7
351#define CONTROL2_LOWPWR_SHIFT 0
352#define CONTROL2_ADCEN_SHIFT 1
353#define CONTROL2_CPEN_SHIFT 2
354#define CONTROL2_ACC_DET_SHIFT 5
355#define CONTROL2_USBCPINT_SHIFT 6
356#define CONTROL2_RCPS_SHIFT 7
357#define CONTROL3_JIGSET_SHIFT 0
358#define CONTROL4_ADCDBSET_SHIFT 0
359#define CONTROL4_USBAUTO_SHIFT 4
360#define CONTROL4_FCTAUTO_SHIFT 5
361#define CONTROL4_ADCMODE_SHIFT 6
362
363#define MAX77843_MUIC_CONTROL1_COMP1SW_MASK (0x7 << CONTROL1_COMP1SW_SHIFT)
364#define MAX77843_MUIC_CONTROL1_COMP2SW_MASK (0x7 << CONTROL1_COMP2SW_SHIFT)
365#define MAX77843_MUIC_CONTROL1_IDBEN_MASK BIT(CONTROL1_IDBEN_SHIFT)
366#define MAX77843_MUIC_CONTROL2_LOWPWR_MASK BIT(CONTROL2_LOWPWR_SHIFT)
367#define MAX77843_MUIC_CONTROL2_ADCEN_MASK BIT(CONTROL2_ADCEN_SHIFT)
368#define MAX77843_MUIC_CONTROL2_CPEN_MASK BIT(CONTROL2_CPEN_SHIFT)
369#define MAX77843_MUIC_CONTROL2_ACC_DET_MASK BIT(CONTROL2_ACC_DET_SHIFT)
370#define MAX77843_MUIC_CONTROL2_USBCPINT_MASK BIT(CONTROL2_USBCPINT_SHIFT)
371#define MAX77843_MUIC_CONTROL2_RCPS_MASK BIT(CONTROL2_RCPS_SHIFT)
372#define MAX77843_MUIC_CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
373#define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK (0x3 << CONTROL4_ADCDBSET_SHIFT)
374#define MAX77843_MUIC_CONTROL4_USBAUTO_MASK BIT(CONTROL4_USBAUTO_SHIFT)
375#define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK BIT(CONTROL4_FCTAUTO_SHIFT)
376#define MAX77843_MUIC_CONTROL4_ADCMODE_MASK (0x3 << CONTROL4_ADCMODE_SHIFT)
377
378/* MAX77843 switch port */
379#define COM_OPEN 0
380#define COM_USB 1
381#define COM_AUDIO 2
382#define COM_UART 3
383#define COM_AUX_USB 4
384#define COM_AUX_UART 5
385
386#define CONTROL1_COM_SW \
387 ((MAX77843_MUIC_CONTROL1_COMP1SW_MASK | \
388 MAX77843_MUIC_CONTROL1_COMP2SW_MASK))
389
390#define CONTROL1_SW_OPEN \
391 ((COM_OPEN << CONTROL1_COMP1SW_SHIFT | \
392 COM_OPEN << CONTROL1_COMP2SW_SHIFT))
393#define CONTROL1_SW_USB \
394 ((COM_USB << CONTROL1_COMP1SW_SHIFT | \
395 COM_USB << CONTROL1_COMP2SW_SHIFT))
396#define CONTROL1_SW_AUDIO \
397 ((COM_AUDIO << CONTROL1_COMP1SW_SHIFT | \
398 COM_AUDIO << CONTROL1_COMP2SW_SHIFT))
399#define CONTROL1_SW_UART \
400 ((COM_UART << CONTROL1_COMP1SW_SHIFT | \
401 COM_UART << CONTROL1_COMP2SW_SHIFT))
402#define CONTROL1_SW_AUX_USB \
403 ((COM_AUX_USB << CONTROL1_COMP1SW_SHIFT | \
404 COM_AUX_USB << CONTROL1_COMP2SW_SHIFT))
405#define CONTROL1_SW_AUX_UART \
406 ((COM_AUX_UART << CONTROL1_COMP1SW_SHIFT | \
407 COM_AUX_UART << CONTROL1_COMP2SW_SHIFT))
408
409#define MAX77843_DISABLE 0
410#define MAX77843_ENABLE 1
411
412#define CONTROL4_AUTO_DISABLE \
413 ((MAX77843_DISABLE << CONTROL4_USBAUTO_SHIFT) | \
414 (MAX77843_DISABLE << CONTROL4_FCTAUTO_SHIFT))
415#define CONTROL4_AUTO_ENABLE \
416 ((MAX77843_ENABLE << CONTROL4_USBAUTO_SHIFT) | \
417 (MAX77843_ENABLE << CONTROL4_FCTAUTO_SHIFT))
418
419/* MAX77843 SAFEOUT LDO Control register */
420#define SAFEOUTCTRL_SAFEOUT1_SHIFT 0
421#define SAFEOUTCTRL_SAFEOUT2_SHIFT 2
422#define SAFEOUTCTRL_ENSAFEOUT1_SHIFT 6
423#define SAFEOUTCTRL_ENSAFEOUT2_SHIFT 7
424
425#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT1 \
426 BIT(SAFEOUTCTRL_ENSAFEOUT1_SHIFT)
427#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT2 \
428 BIT(SAFEOUTCTRL_ENSAFEOUT2_SHIFT)
429#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT1_MASK \
430 (0x3 << SAFEOUTCTRL_SAFEOUT1_SHIFT)
431#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT2_MASK \
432 (0x3 << SAFEOUTCTRL_SAFEOUT2_SHIFT)
433
434struct max77843 {
435 struct device *dev;
436
437 struct i2c_client *i2c;
438 struct i2c_client *i2c_chg;
439 struct i2c_client *i2c_fuel;
440 struct i2c_client *i2c_muic;
441
442 struct regmap *regmap;
443 struct regmap *regmap_chg;
444 struct regmap *regmap_fuel;
445 struct regmap *regmap_muic;
446
447 struct regmap_irq_chip_data *irq_data;
448 struct regmap_irq_chip_data *irq_data_chg;
449 struct regmap_irq_chip_data *irq_data_fuel;
450 struct regmap_irq_chip_data *irq_data_muic;
451
452 int irq;
453};
454#endif /* __MAX77843_H__ */
diff --git a/include/linux/mfd/menelaus.h b/include/linux/mfd/menelaus.h
index f097e89134cb..9e85ac06da89 100644
--- a/include/linux/mfd/menelaus.h
+++ b/include/linux/mfd/menelaus.h
@@ -24,7 +24,6 @@ extern int menelaus_set_vaux(unsigned int mV);
24extern int menelaus_set_vdcdc(int dcdc, unsigned int mV); 24extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
25extern int menelaus_set_slot_sel(int enable); 25extern int menelaus_set_slot_sel(int enable);
26extern int menelaus_get_slot_pin_states(void); 26extern int menelaus_get_slot_pin_states(void);
27extern int menelaus_set_vcore_sw(unsigned int mV);
28extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV); 27extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
29 28
30#define EN_VPLL_SLEEP (1 << 7) 29#define EN_VPLL_SLEEP (1 << 7)
@@ -38,10 +37,4 @@ extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
38 37
39extern int menelaus_set_regulator_sleep(int enable, u32 val); 38extern int menelaus_set_regulator_sleep(int enable, u32 val);
40 39
41#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS)
42#define omap_has_menelaus() 1
43#else
44#define omap_has_menelaus() 0
45#endif
46
47#endif 40#endif
diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
new file mode 100644
index 000000000000..cf5265b0d1c1
--- /dev/null
+++ b/include/linux/mfd/mt6397/core.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MFD_MT6397_CORE_H__
16#define __MFD_MT6397_CORE_H__
17
18enum mt6397_irq_numbers {
19 MT6397_IRQ_SPKL_AB = 0,
20 MT6397_IRQ_SPKR_AB,
21 MT6397_IRQ_SPKL,
22 MT6397_IRQ_SPKR,
23 MT6397_IRQ_BAT_L,
24 MT6397_IRQ_BAT_H,
25 MT6397_IRQ_FG_BAT_L,
26 MT6397_IRQ_FG_BAT_H,
27 MT6397_IRQ_WATCHDOG,
28 MT6397_IRQ_PWRKEY,
29 MT6397_IRQ_THR_L,
30 MT6397_IRQ_THR_H,
31 MT6397_IRQ_VBATON_UNDET,
32 MT6397_IRQ_BVALID_DET,
33 MT6397_IRQ_CHRDET,
34 MT6397_IRQ_OV,
35 MT6397_IRQ_LDO,
36 MT6397_IRQ_HOMEKEY,
37 MT6397_IRQ_ACCDET,
38 MT6397_IRQ_AUDIO,
39 MT6397_IRQ_RTC,
40 MT6397_IRQ_PWRKEY_RSTB,
41 MT6397_IRQ_HDMI_SIFM,
42 MT6397_IRQ_HDMI_CEC,
43 MT6397_IRQ_VCA15,
44 MT6397_IRQ_VSRMCA15,
45 MT6397_IRQ_VCORE,
46 MT6397_IRQ_VGPU,
47 MT6397_IRQ_VIO18,
48 MT6397_IRQ_VPCA7,
49 MT6397_IRQ_VSRMCA7,
50 MT6397_IRQ_VDRM,
51 MT6397_IRQ_NR,
52};
53
54struct mt6397_chip {
55 struct device *dev;
56 struct regmap *regmap;
57 int irq;
58 struct irq_domain *irq_domain;
59 struct mutex irqlock;
60 u16 irq_masks_cur[2];
61 u16 irq_masks_cache[2];
62};
63
64#endif /* __MFD_MT6397_CORE_H__ */
diff --git a/include/linux/mfd/mt6397/registers.h b/include/linux/mfd/mt6397/registers.h
new file mode 100644
index 000000000000..f23a0a60a877
--- /dev/null
+++ b/include/linux/mfd/mt6397/registers.h
@@ -0,0 +1,362 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MFD_MT6397_REGISTERS_H__
16#define __MFD_MT6397_REGISTERS_H__
17
18/* PMIC Registers */
19#define MT6397_CID 0x0100
20#define MT6397_TOP_CKPDN 0x0102
21#define MT6397_TOP_CKPDN_SET 0x0104
22#define MT6397_TOP_CKPDN_CLR 0x0106
23#define MT6397_TOP_CKPDN2 0x0108
24#define MT6397_TOP_CKPDN2_SET 0x010A
25#define MT6397_TOP_CKPDN2_CLR 0x010C
26#define MT6397_TOP_GPIO_CKPDN 0x010E
27#define MT6397_TOP_RST_CON 0x0114
28#define MT6397_WRP_CKPDN 0x011A
29#define MT6397_WRP_RST_CON 0x0120
30#define MT6397_TOP_RST_MISC 0x0126
31#define MT6397_TOP_CKCON1 0x0128
32#define MT6397_TOP_CKCON2 0x012A
33#define MT6397_TOP_CKTST1 0x012C
34#define MT6397_TOP_CKTST2 0x012E
35#define MT6397_OC_DEG_EN 0x0130
36#define MT6397_OC_CTL0 0x0132
37#define MT6397_OC_CTL1 0x0134
38#define MT6397_OC_CTL2 0x0136
39#define MT6397_INT_RSV 0x0138
40#define MT6397_TEST_CON0 0x013A
41#define MT6397_TEST_CON1 0x013C
42#define MT6397_STATUS0 0x013E
43#define MT6397_STATUS1 0x0140
44#define MT6397_PGSTATUS 0x0142
45#define MT6397_CHRSTATUS 0x0144
46#define MT6397_OCSTATUS0 0x0146
47#define MT6397_OCSTATUS1 0x0148
48#define MT6397_OCSTATUS2 0x014A
49#define MT6397_HDMI_PAD_IE 0x014C
50#define MT6397_TEST_OUT_L 0x014E
51#define MT6397_TEST_OUT_H 0x0150
52#define MT6397_TDSEL_CON 0x0152
53#define MT6397_RDSEL_CON 0x0154
54#define MT6397_GPIO_SMT_CON0 0x0156
55#define MT6397_GPIO_SMT_CON1 0x0158
56#define MT6397_GPIO_SMT_CON2 0x015A
57#define MT6397_GPIO_SMT_CON3 0x015C
58#define MT6397_DRV_CON0 0x015E
59#define MT6397_DRV_CON1 0x0160
60#define MT6397_DRV_CON2 0x0162
61#define MT6397_DRV_CON3 0x0164
62#define MT6397_DRV_CON4 0x0166
63#define MT6397_DRV_CON5 0x0168
64#define MT6397_DRV_CON6 0x016A
65#define MT6397_DRV_CON7 0x016C
66#define MT6397_DRV_CON8 0x016E
67#define MT6397_DRV_CON9 0x0170
68#define MT6397_DRV_CON10 0x0172
69#define MT6397_DRV_CON11 0x0174
70#define MT6397_DRV_CON12 0x0176
71#define MT6397_INT_CON0 0x0178
72#define MT6397_INT_CON1 0x017E
73#define MT6397_INT_STATUS0 0x0184
74#define MT6397_INT_STATUS1 0x0186
75#define MT6397_FQMTR_CON0 0x0188
76#define MT6397_FQMTR_CON1 0x018A
77#define MT6397_FQMTR_CON2 0x018C
78#define MT6397_EFUSE_DOUT_0_15 0x01C4
79#define MT6397_EFUSE_DOUT_16_31 0x01C6
80#define MT6397_EFUSE_DOUT_32_47 0x01C8
81#define MT6397_EFUSE_DOUT_48_63 0x01CA
82#define MT6397_SPI_CON 0x01CC
83#define MT6397_TOP_CKPDN3 0x01CE
84#define MT6397_TOP_CKCON3 0x01D4
85#define MT6397_EFUSE_DOUT_64_79 0x01D6
86#define MT6397_EFUSE_DOUT_80_95 0x01D8
87#define MT6397_EFUSE_DOUT_96_111 0x01DA
88#define MT6397_EFUSE_DOUT_112_127 0x01DC
89#define MT6397_EFUSE_DOUT_128_143 0x01DE
90#define MT6397_EFUSE_DOUT_144_159 0x01E0
91#define MT6397_EFUSE_DOUT_160_175 0x01E2
92#define MT6397_EFUSE_DOUT_176_191 0x01E4
93#define MT6397_EFUSE_DOUT_192_207 0x01E6
94#define MT6397_EFUSE_DOUT_208_223 0x01E8
95#define MT6397_EFUSE_DOUT_224_239 0x01EA
96#define MT6397_EFUSE_DOUT_240_255 0x01EC
97#define MT6397_EFUSE_DOUT_256_271 0x01EE
98#define MT6397_EFUSE_DOUT_272_287 0x01F0
99#define MT6397_EFUSE_DOUT_288_300 0x01F2
100#define MT6397_EFUSE_DOUT_304_319 0x01F4
101#define MT6397_BUCK_CON0 0x0200
102#define MT6397_BUCK_CON1 0x0202
103#define MT6397_BUCK_CON2 0x0204
104#define MT6397_BUCK_CON3 0x0206
105#define MT6397_BUCK_CON4 0x0208
106#define MT6397_BUCK_CON5 0x020A
107#define MT6397_BUCK_CON6 0x020C
108#define MT6397_BUCK_CON7 0x020E
109#define MT6397_BUCK_CON8 0x0210
110#define MT6397_BUCK_CON9 0x0212
111#define MT6397_VCA15_CON0 0x0214
112#define MT6397_VCA15_CON1 0x0216
113#define MT6397_VCA15_CON2 0x0218
114#define MT6397_VCA15_CON3 0x021A
115#define MT6397_VCA15_CON4 0x021C
116#define MT6397_VCA15_CON5 0x021E
117#define MT6397_VCA15_CON6 0x0220
118#define MT6397_VCA15_CON7 0x0222
119#define MT6397_VCA15_CON8 0x0224
120#define MT6397_VCA15_CON9 0x0226
121#define MT6397_VCA15_CON10 0x0228
122#define MT6397_VCA15_CON11 0x022A
123#define MT6397_VCA15_CON12 0x022C
124#define MT6397_VCA15_CON13 0x022E
125#define MT6397_VCA15_CON14 0x0230
126#define MT6397_VCA15_CON15 0x0232
127#define MT6397_VCA15_CON16 0x0234
128#define MT6397_VCA15_CON17 0x0236
129#define MT6397_VCA15_CON18 0x0238
130#define MT6397_VSRMCA15_CON0 0x023A
131#define MT6397_VSRMCA15_CON1 0x023C
132#define MT6397_VSRMCA15_CON2 0x023E
133#define MT6397_VSRMCA15_CON3 0x0240
134#define MT6397_VSRMCA15_CON4 0x0242
135#define MT6397_VSRMCA15_CON5 0x0244
136#define MT6397_VSRMCA15_CON6 0x0246
137#define MT6397_VSRMCA15_CON7 0x0248
138#define MT6397_VSRMCA15_CON8 0x024A
139#define MT6397_VSRMCA15_CON9 0x024C
140#define MT6397_VSRMCA15_CON10 0x024E
141#define MT6397_VSRMCA15_CON11 0x0250
142#define MT6397_VSRMCA15_CON12 0x0252
143#define MT6397_VSRMCA15_CON13 0x0254
144#define MT6397_VSRMCA15_CON14 0x0256
145#define MT6397_VSRMCA15_CON15 0x0258
146#define MT6397_VSRMCA15_CON16 0x025A
147#define MT6397_VSRMCA15_CON17 0x025C
148#define MT6397_VSRMCA15_CON18 0x025E
149#define MT6397_VSRMCA15_CON19 0x0260
150#define MT6397_VSRMCA15_CON20 0x0262
151#define MT6397_VSRMCA15_CON21 0x0264
152#define MT6397_VCORE_CON0 0x0266
153#define MT6397_VCORE_CON1 0x0268
154#define MT6397_VCORE_CON2 0x026A
155#define MT6397_VCORE_CON3 0x026C
156#define MT6397_VCORE_CON4 0x026E
157#define MT6397_VCORE_CON5 0x0270
158#define MT6397_VCORE_CON6 0x0272
159#define MT6397_VCORE_CON7 0x0274
160#define MT6397_VCORE_CON8 0x0276
161#define MT6397_VCORE_CON9 0x0278
162#define MT6397_VCORE_CON10 0x027A
163#define MT6397_VCORE_CON11 0x027C
164#define MT6397_VCORE_CON12 0x027E
165#define MT6397_VCORE_CON13 0x0280
166#define MT6397_VCORE_CON14 0x0282
167#define MT6397_VCORE_CON15 0x0284
168#define MT6397_VCORE_CON16 0x0286
169#define MT6397_VCORE_CON17 0x0288
170#define MT6397_VCORE_CON18 0x028A
171#define MT6397_VGPU_CON0 0x028C
172#define MT6397_VGPU_CON1 0x028E
173#define MT6397_VGPU_CON2 0x0290
174#define MT6397_VGPU_CON3 0x0292
175#define MT6397_VGPU_CON4 0x0294
176#define MT6397_VGPU_CON5 0x0296
177#define MT6397_VGPU_CON6 0x0298
178#define MT6397_VGPU_CON7 0x029A
179#define MT6397_VGPU_CON8 0x029C
180#define MT6397_VGPU_CON9 0x029E
181#define MT6397_VGPU_CON10 0x02A0
182#define MT6397_VGPU_CON11 0x02A2
183#define MT6397_VGPU_CON12 0x02A4
184#define MT6397_VGPU_CON13 0x02A6
185#define MT6397_VGPU_CON14 0x02A8
186#define MT6397_VGPU_CON15 0x02AA
187#define MT6397_VGPU_CON16 0x02AC
188#define MT6397_VGPU_CON17 0x02AE
189#define MT6397_VGPU_CON18 0x02B0
190#define MT6397_VIO18_CON0 0x0300
191#define MT6397_VIO18_CON1 0x0302
192#define MT6397_VIO18_CON2 0x0304
193#define MT6397_VIO18_CON3 0x0306
194#define MT6397_VIO18_CON4 0x0308
195#define MT6397_VIO18_CON5 0x030A
196#define MT6397_VIO18_CON6 0x030C
197#define MT6397_VIO18_CON7 0x030E
198#define MT6397_VIO18_CON8 0x0310
199#define MT6397_VIO18_CON9 0x0312
200#define MT6397_VIO18_CON10 0x0314
201#define MT6397_VIO18_CON11 0x0316
202#define MT6397_VIO18_CON12 0x0318
203#define MT6397_VIO18_CON13 0x031A
204#define MT6397_VIO18_CON14 0x031C
205#define MT6397_VIO18_CON15 0x031E
206#define MT6397_VIO18_CON16 0x0320
207#define MT6397_VIO18_CON17 0x0322
208#define MT6397_VIO18_CON18 0x0324
209#define MT6397_VPCA7_CON0 0x0326
210#define MT6397_VPCA7_CON1 0x0328
211#define MT6397_VPCA7_CON2 0x032A
212#define MT6397_VPCA7_CON3 0x032C
213#define MT6397_VPCA7_CON4 0x032E
214#define MT6397_VPCA7_CON5 0x0330
215#define MT6397_VPCA7_CON6 0x0332
216#define MT6397_VPCA7_CON7 0x0334
217#define MT6397_VPCA7_CON8 0x0336
218#define MT6397_VPCA7_CON9 0x0338
219#define MT6397_VPCA7_CON10 0x033A
220#define MT6397_VPCA7_CON11 0x033C
221#define MT6397_VPCA7_CON12 0x033E
222#define MT6397_VPCA7_CON13 0x0340
223#define MT6397_VPCA7_CON14 0x0342
224#define MT6397_VPCA7_CON15 0x0344
225#define MT6397_VPCA7_CON16 0x0346
226#define MT6397_VPCA7_CON17 0x0348
227#define MT6397_VPCA7_CON18 0x034A
228#define MT6397_VSRMCA7_CON0 0x034C
229#define MT6397_VSRMCA7_CON1 0x034E
230#define MT6397_VSRMCA7_CON2 0x0350
231#define MT6397_VSRMCA7_CON3 0x0352
232#define MT6397_VSRMCA7_CON4 0x0354
233#define MT6397_VSRMCA7_CON5 0x0356
234#define MT6397_VSRMCA7_CON6 0x0358
235#define MT6397_VSRMCA7_CON7 0x035A
236#define MT6397_VSRMCA7_CON8 0x035C
237#define MT6397_VSRMCA7_CON9 0x035E
238#define MT6397_VSRMCA7_CON10 0x0360
239#define MT6397_VSRMCA7_CON11 0x0362
240#define MT6397_VSRMCA7_CON12 0x0364
241#define MT6397_VSRMCA7_CON13 0x0366
242#define MT6397_VSRMCA7_CON14 0x0368
243#define MT6397_VSRMCA7_CON15 0x036A
244#define MT6397_VSRMCA7_CON16 0x036C
245#define MT6397_VSRMCA7_CON17 0x036E
246#define MT6397_VSRMCA7_CON18 0x0370
247#define MT6397_VSRMCA7_CON19 0x0372
248#define MT6397_VSRMCA7_CON20 0x0374
249#define MT6397_VSRMCA7_CON21 0x0376
250#define MT6397_VDRM_CON0 0x0378
251#define MT6397_VDRM_CON1 0x037A
252#define MT6397_VDRM_CON2 0x037C
253#define MT6397_VDRM_CON3 0x037E
254#define MT6397_VDRM_CON4 0x0380
255#define MT6397_VDRM_CON5 0x0382
256#define MT6397_VDRM_CON6 0x0384
257#define MT6397_VDRM_CON7 0x0386
258#define MT6397_VDRM_CON8 0x0388
259#define MT6397_VDRM_CON9 0x038A
260#define MT6397_VDRM_CON10 0x038C
261#define MT6397_VDRM_CON11 0x038E
262#define MT6397_VDRM_CON12 0x0390
263#define MT6397_VDRM_CON13 0x0392
264#define MT6397_VDRM_CON14 0x0394
265#define MT6397_VDRM_CON15 0x0396
266#define MT6397_VDRM_CON16 0x0398
267#define MT6397_VDRM_CON17 0x039A
268#define MT6397_VDRM_CON18 0x039C
269#define MT6397_BUCK_K_CON0 0x039E
270#define MT6397_BUCK_K_CON1 0x03A0
271#define MT6397_ANALDO_CON0 0x0400
272#define MT6397_ANALDO_CON1 0x0402
273#define MT6397_ANALDO_CON2 0x0404
274#define MT6397_ANALDO_CON3 0x0406
275#define MT6397_ANALDO_CON4 0x0408
276#define MT6397_ANALDO_CON5 0x040A
277#define MT6397_ANALDO_CON6 0x040C
278#define MT6397_ANALDO_CON7 0x040E
279#define MT6397_DIGLDO_CON0 0x0410
280#define MT6397_DIGLDO_CON1 0x0412
281#define MT6397_DIGLDO_CON2 0x0414
282#define MT6397_DIGLDO_CON3 0x0416
283#define MT6397_DIGLDO_CON4 0x0418
284#define MT6397_DIGLDO_CON5 0x041A
285#define MT6397_DIGLDO_CON6 0x041C
286#define MT6397_DIGLDO_CON7 0x041E
287#define MT6397_DIGLDO_CON8 0x0420
288#define MT6397_DIGLDO_CON9 0x0422
289#define MT6397_DIGLDO_CON10 0x0424
290#define MT6397_DIGLDO_CON11 0x0426
291#define MT6397_DIGLDO_CON12 0x0428
292#define MT6397_DIGLDO_CON13 0x042A
293#define MT6397_DIGLDO_CON14 0x042C
294#define MT6397_DIGLDO_CON15 0x042E
295#define MT6397_DIGLDO_CON16 0x0430
296#define MT6397_DIGLDO_CON17 0x0432
297#define MT6397_DIGLDO_CON18 0x0434
298#define MT6397_DIGLDO_CON19 0x0436
299#define MT6397_DIGLDO_CON20 0x0438
300#define MT6397_DIGLDO_CON21 0x043A
301#define MT6397_DIGLDO_CON22 0x043C
302#define MT6397_DIGLDO_CON23 0x043E
303#define MT6397_DIGLDO_CON24 0x0440
304#define MT6397_DIGLDO_CON25 0x0442
305#define MT6397_DIGLDO_CON26 0x0444
306#define MT6397_DIGLDO_CON27 0x0446
307#define MT6397_DIGLDO_CON28 0x0448
308#define MT6397_DIGLDO_CON29 0x044A
309#define MT6397_DIGLDO_CON30 0x044C
310#define MT6397_DIGLDO_CON31 0x044E
311#define MT6397_DIGLDO_CON32 0x0450
312#define MT6397_DIGLDO_CON33 0x045A
313#define MT6397_SPK_CON0 0x0600
314#define MT6397_SPK_CON1 0x0602
315#define MT6397_SPK_CON2 0x0604
316#define MT6397_SPK_CON3 0x0606
317#define MT6397_SPK_CON4 0x0608
318#define MT6397_SPK_CON5 0x060A
319#define MT6397_SPK_CON6 0x060C
320#define MT6397_SPK_CON7 0x060E
321#define MT6397_SPK_CON8 0x0610
322#define MT6397_SPK_CON9 0x0612
323#define MT6397_SPK_CON10 0x0614
324#define MT6397_SPK_CON11 0x0616
325#define MT6397_AUDDAC_CON0 0x0700
326#define MT6397_AUDBUF_CFG0 0x0702
327#define MT6397_AUDBUF_CFG1 0x0704
328#define MT6397_AUDBUF_CFG2 0x0706
329#define MT6397_AUDBUF_CFG3 0x0708
330#define MT6397_AUDBUF_CFG4 0x070A
331#define MT6397_IBIASDIST_CFG0 0x070C
332#define MT6397_AUDACCDEPOP_CFG0 0x070E
333#define MT6397_AUD_IV_CFG0 0x0710
334#define MT6397_AUDCLKGEN_CFG0 0x0712
335#define MT6397_AUDLDO_CFG0 0x0714
336#define MT6397_AUDLDO_CFG1 0x0716
337#define MT6397_AUDNVREGGLB_CFG0 0x0718
338#define MT6397_AUD_NCP0 0x071A
339#define MT6397_AUDPREAMP_CON0 0x071C
340#define MT6397_AUDADC_CON0 0x071E
341#define MT6397_AUDADC_CON1 0x0720
342#define MT6397_AUDADC_CON2 0x0722
343#define MT6397_AUDADC_CON3 0x0724
344#define MT6397_AUDADC_CON4 0x0726
345#define MT6397_AUDADC_CON5 0x0728
346#define MT6397_AUDADC_CON6 0x072A
347#define MT6397_AUDDIGMI_CON0 0x072C
348#define MT6397_AUDLSBUF_CON0 0x072E
349#define MT6397_AUDLSBUF_CON1 0x0730
350#define MT6397_AUDENCSPARE_CON0 0x0732
351#define MT6397_AUDENCCLKSQ_CON0 0x0734
352#define MT6397_AUDPREAMPGAIN_CON0 0x0736
353#define MT6397_ZCD_CON0 0x0738
354#define MT6397_ZCD_CON1 0x073A
355#define MT6397_ZCD_CON2 0x073C
356#define MT6397_ZCD_CON3 0x073E
357#define MT6397_ZCD_CON4 0x0740
358#define MT6397_ZCD_CON5 0x0742
359#define MT6397_NCP_CLKDIV_CON0 0x0744
360#define MT6397_NCP_CLKDIV_CON1 0x0746
361
362#endif /* __MFD_MT6397_REGISTERS_H__ */
diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h
index fb09312d854b..441b6ee72691 100644
--- a/include/linux/mfd/rk808.h
+++ b/include/linux/mfd/rk808.h
@@ -156,6 +156,9 @@ enum rk808_reg {
156#define BUCK2_RATE_MASK (3 << 3) 156#define BUCK2_RATE_MASK (3 << 3)
157#define MASK_ALL 0xff 157#define MASK_ALL 0xff
158 158
159#define BUCK_UV_ACT_MASK 0x0f
160#define BUCK_UV_ACT_DISABLE 0
161
159#define SWITCH2_EN BIT(6) 162#define SWITCH2_EN BIT(6)
160#define SWITCH1_EN BIT(5) 163#define SWITCH1_EN BIT(5)
161#define DEV_OFF_RST BIT(3) 164#define DEV_OFF_RST BIT(3)
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index 0c12628e91c6..ff843e7ca23d 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -28,74 +28,72 @@
28 28
29#define MAX_RW_REG_CNT 1024 29#define MAX_RW_REG_CNT 1024
30 30
31/* PCI Operation Register Address */
32#define RTSX_HCBAR 0x00 31#define RTSX_HCBAR 0x00
33#define RTSX_HCBCTLR 0x04 32#define RTSX_HCBCTLR 0x04
33#define STOP_CMD (0x01 << 28)
34#define READ_REG_CMD 0
35#define WRITE_REG_CMD 1
36#define CHECK_REG_CMD 2
37
34#define RTSX_HDBAR 0x08 38#define RTSX_HDBAR 0x08
39#define SG_INT 0x04
40#define SG_END 0x02
41#define SG_VALID 0x01
42#define SG_NO_OP 0x00
43#define SG_TRANS_DATA (0x02 << 4)
44#define SG_LINK_DESC (0x03 << 4)
35#define RTSX_HDBCTLR 0x0C 45#define RTSX_HDBCTLR 0x0C
46#define SDMA_MODE 0x00
47#define ADMA_MODE (0x02 << 26)
48#define STOP_DMA (0x01 << 28)
49#define TRIG_DMA (0x01 << 31)
50
36#define RTSX_HAIMR 0x10 51#define RTSX_HAIMR 0x10
37#define RTSX_BIPR 0x14 52#define HAIMR_TRANS_START (0x01 << 31)
38#define RTSX_BIER 0x18 53#define HAIMR_READ 0x00
54#define HAIMR_WRITE (0x01 << 30)
55#define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ)
56#define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE)
57#define HAIMR_TRANS_END (HAIMR_TRANS_START)
39 58
40/* Host command buffer control register */ 59#define RTSX_BIPR 0x14
41#define STOP_CMD (0x01 << 28) 60#define CMD_DONE_INT (1 << 31)
42 61#define DATA_DONE_INT (1 << 30)
43/* Host data buffer control register */ 62#define TRANS_OK_INT (1 << 29)
44#define SDMA_MODE 0x00 63#define TRANS_FAIL_INT (1 << 28)
45#define ADMA_MODE (0x02 << 26) 64#define XD_INT (1 << 27)
46#define STOP_DMA (0x01 << 28) 65#define MS_INT (1 << 26)
47#define TRIG_DMA (0x01 << 31) 66#define SD_INT (1 << 25)
48 67#define GPIO0_INT (1 << 24)
49/* Host access internal memory register */ 68#define OC_INT (1 << 23)
50#define HAIMR_TRANS_START (0x01 << 31) 69#define SD_WRITE_PROTECT (1 << 19)
51#define HAIMR_READ 0x00 70#define XD_EXIST (1 << 18)
52#define HAIMR_WRITE (0x01 << 30) 71#define MS_EXIST (1 << 17)
53#define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ) 72#define SD_EXIST (1 << 16)
54#define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE) 73#define DELINK_INT GPIO0_INT
55#define HAIMR_TRANS_END (HAIMR_TRANS_START) 74#define MS_OC_INT (1 << 23)
56 75#define SD_OC_INT (1 << 22)
57/* Bus interrupt pending register */
58#define CMD_DONE_INT (1 << 31)
59#define DATA_DONE_INT (1 << 30)
60#define TRANS_OK_INT (1 << 29)
61#define TRANS_FAIL_INT (1 << 28)
62#define XD_INT (1 << 27)
63#define MS_INT (1 << 26)
64#define SD_INT (1 << 25)
65#define GPIO0_INT (1 << 24)
66#define OC_INT (1 << 23)
67#define SD_WRITE_PROTECT (1 << 19)
68#define XD_EXIST (1 << 18)
69#define MS_EXIST (1 << 17)
70#define SD_EXIST (1 << 16)
71#define DELINK_INT GPIO0_INT
72#define MS_OC_INT (1 << 23)
73#define SD_OC_INT (1 << 22)
74 76
75#define CARD_INT (XD_INT | MS_INT | SD_INT) 77#define CARD_INT (XD_INT | MS_INT | SD_INT)
76#define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT) 78#define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
77#define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \ 79#define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \
78 CARD_INT | GPIO0_INT | OC_INT) 80 CARD_INT | GPIO0_INT | OC_INT)
79
80#define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST) 81#define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST)
81 82
82/* Bus interrupt enable register */ 83#define RTSX_BIER 0x18
83#define CMD_DONE_INT_EN (1 << 31) 84#define CMD_DONE_INT_EN (1 << 31)
84#define DATA_DONE_INT_EN (1 << 30) 85#define DATA_DONE_INT_EN (1 << 30)
85#define TRANS_OK_INT_EN (1 << 29) 86#define TRANS_OK_INT_EN (1 << 29)
86#define TRANS_FAIL_INT_EN (1 << 28) 87#define TRANS_FAIL_INT_EN (1 << 28)
87#define XD_INT_EN (1 << 27) 88#define XD_INT_EN (1 << 27)
88#define MS_INT_EN (1 << 26) 89#define MS_INT_EN (1 << 26)
89#define SD_INT_EN (1 << 25) 90#define SD_INT_EN (1 << 25)
90#define GPIO0_INT_EN (1 << 24) 91#define GPIO0_INT_EN (1 << 24)
91#define OC_INT_EN (1 << 23) 92#define OC_INT_EN (1 << 23)
92#define DELINK_INT_EN GPIO0_INT_EN 93#define DELINK_INT_EN GPIO0_INT_EN
93#define MS_OC_INT_EN (1 << 23) 94#define MS_OC_INT_EN (1 << 23)
94#define SD_OC_INT_EN (1 << 22) 95#define SD_OC_INT_EN (1 << 22)
95 96
96#define READ_REG_CMD 0
97#define WRITE_REG_CMD 1
98#define CHECK_REG_CMD 2
99 97
100/* 98/*
101 * macros for easy use 99 * macros for easy use
@@ -125,423 +123,68 @@
125#define rtsx_pci_write_config_dword(pcr, where, val) \ 123#define rtsx_pci_write_config_dword(pcr, where, val) \
126 pci_write_config_dword((pcr)->pci, where, val) 124 pci_write_config_dword((pcr)->pci, where, val)
127 125
128#define STATE_TRANS_NONE 0 126#define STATE_TRANS_NONE 0
129#define STATE_TRANS_CMD 1 127#define STATE_TRANS_CMD 1
130#define STATE_TRANS_BUF 2 128#define STATE_TRANS_BUF 2
131#define STATE_TRANS_SG 3 129#define STATE_TRANS_SG 3
132
133#define TRANS_NOT_READY 0
134#define TRANS_RESULT_OK 1
135#define TRANS_RESULT_FAIL 2
136#define TRANS_NO_DEVICE 3
137
138#define RTSX_RESV_BUF_LEN 4096
139#define HOST_CMDS_BUF_LEN 1024
140#define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
141#define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8)
142#define MAX_SG_ITEM_LEN 0x80000
143
144#define HOST_TO_DEVICE 0
145#define DEVICE_TO_HOST 1
146
147#define RTSX_PHASE_MAX 32
148#define RX_TUNING_CNT 3
149
150/* SG descriptor */
151#define SG_INT 0x04
152#define SG_END 0x02
153#define SG_VALID 0x01
154
155#define SG_NO_OP 0x00
156#define SG_TRANS_DATA (0x02 << 4)
157#define SG_LINK_DESC (0x03 << 4)
158
159/* Output voltage */
160#define OUTPUT_3V3 0
161#define OUTPUT_1V8 1
162
163/* Card Clock Enable Register */
164#define SD_CLK_EN 0x04
165#define MS_CLK_EN 0x08
166
167/* Card Select Register */
168#define SD_MOD_SEL 2
169#define MS_MOD_SEL 3
170
171/* Card Output Enable Register */
172#define SD_OUTPUT_EN 0x04
173#define MS_OUTPUT_EN 0x08
174
175/* CARD_SHARE_MODE */
176#define CARD_SHARE_MASK 0x0F
177#define CARD_SHARE_MULTI_LUN 0x00
178#define CARD_SHARE_NORMAL 0x00
179#define CARD_SHARE_48_SD 0x04
180#define CARD_SHARE_48_MS 0x08
181/* CARD_SHARE_MODE for barossa */
182#define CARD_SHARE_BAROSSA_SD 0x01
183#define CARD_SHARE_BAROSSA_MS 0x02
184
185/* CARD_DRIVE_SEL */
186#define MS_DRIVE_8mA (0x01 << 6)
187#define MMC_DRIVE_8mA (0x01 << 4)
188#define XD_DRIVE_8mA (0x01 << 2)
189#define GPIO_DRIVE_8mA 0x01
190#define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
191 XD_DRIVE_8mA | GPIO_DRIVE_8mA)
192#define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
193 XD_DRIVE_8mA)
194#define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA)
195 130
196/* SD30_DRIVE_SEL */ 131#define TRANS_NOT_READY 0
197#define DRIVER_TYPE_A 0x05 132#define TRANS_RESULT_OK 1
198#define DRIVER_TYPE_B 0x03 133#define TRANS_RESULT_FAIL 2
199#define DRIVER_TYPE_C 0x02 134#define TRANS_NO_DEVICE 3
200#define DRIVER_TYPE_D 0x01
201#define CFG_DRIVER_TYPE_A 0x02
202#define CFG_DRIVER_TYPE_B 0x03
203#define CFG_DRIVER_TYPE_C 0x01
204#define CFG_DRIVER_TYPE_D 0x00
205
206/* FPDCTL */
207#define SSC_POWER_DOWN 0x01
208#define SD_OC_POWER_DOWN 0x02
209#define ALL_POWER_DOWN 0x07
210#define OC_POWER_DOWN 0x06
211
212/* CLK_CTL */
213#define CHANGE_CLK 0x01
214
215/* LDO_CTL */
216#define BPP_ASIC_1V7 0x00
217#define BPP_ASIC_1V8 0x01
218#define BPP_ASIC_1V9 0x02
219#define BPP_ASIC_2V0 0x03
220#define BPP_ASIC_2V7 0x04
221#define BPP_ASIC_2V8 0x05
222#define BPP_ASIC_3V2 0x06
223#define BPP_ASIC_3V3 0x07
224#define BPP_REG_TUNED18 0x07
225#define BPP_TUNED18_SHIFT_8402 5
226#define BPP_TUNED18_SHIFT_8411 4
227#define BPP_PAD_MASK 0x04
228#define BPP_PAD_3V3 0x04
229#define BPP_PAD_1V8 0x00
230#define BPP_LDO_POWB 0x03
231#define BPP_LDO_ON 0x00
232#define BPP_LDO_SUSPEND 0x02
233#define BPP_LDO_OFF 0x03
234
235/* CD_PAD_CTL */
236#define CD_DISABLE_MASK 0x07
237#define MS_CD_DISABLE 0x04
238#define SD_CD_DISABLE 0x02
239#define XD_CD_DISABLE 0x01
240#define CD_DISABLE 0x07
241#define CD_ENABLE 0x00
242#define MS_CD_EN_ONLY 0x03
243#define SD_CD_EN_ONLY 0x05
244#define XD_CD_EN_ONLY 0x06
245#define FORCE_CD_LOW_MASK 0x38
246#define FORCE_CD_XD_LOW 0x08
247#define FORCE_CD_SD_LOW 0x10
248#define FORCE_CD_MS_LOW 0x20
249#define CD_AUTO_DISABLE 0x40
250
251/* SD_STAT1 */
252#define SD_CRC7_ERR 0x80
253#define SD_CRC16_ERR 0x40
254#define SD_CRC_WRITE_ERR 0x20
255#define SD_CRC_WRITE_ERR_MASK 0x1C
256#define GET_CRC_TIME_OUT 0x02
257#define SD_TUNING_COMPARE_ERR 0x01
258
259/* SD_STAT2 */
260#define SD_RSP_80CLK_TIMEOUT 0x01
261
262/* SD_BUS_STAT */
263#define SD_CLK_TOGGLE_EN 0x80
264#define SD_CLK_FORCE_STOP 0x40
265#define SD_DAT3_STATUS 0x10
266#define SD_DAT2_STATUS 0x08
267#define SD_DAT1_STATUS 0x04
268#define SD_DAT0_STATUS 0x02
269#define SD_CMD_STATUS 0x01
270
271/* SD_PAD_CTL */
272#define SD_IO_USING_1V8 0x80
273#define SD_IO_USING_3V3 0x7F
274#define TYPE_A_DRIVING 0x00
275#define TYPE_B_DRIVING 0x01
276#define TYPE_C_DRIVING 0x02
277#define TYPE_D_DRIVING 0x03
278
279/* SD_SAMPLE_POINT_CTL */
280#define DDR_FIX_RX_DAT 0x00
281#define DDR_VAR_RX_DAT 0x80
282#define DDR_FIX_RX_DAT_EDGE 0x00
283#define DDR_FIX_RX_DAT_14_DELAY 0x40
284#define DDR_FIX_RX_CMD 0x00
285#define DDR_VAR_RX_CMD 0x20
286#define DDR_FIX_RX_CMD_POS_EDGE 0x00
287#define DDR_FIX_RX_CMD_14_DELAY 0x10
288#define SD20_RX_POS_EDGE 0x00
289#define SD20_RX_14_DELAY 0x08
290#define SD20_RX_SEL_MASK 0x08
291 135
292/* SD_PUSH_POINT_CTL */ 136#define RTSX_RESV_BUF_LEN 4096
293#define DDR_FIX_TX_CMD_DAT 0x00 137#define HOST_CMDS_BUF_LEN 1024
294#define DDR_VAR_TX_CMD_DAT 0x80 138#define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
295#define DDR_FIX_TX_DAT_14_TSU 0x00 139#define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8)
296#define DDR_FIX_TX_DAT_12_TSU 0x40 140#define MAX_SG_ITEM_LEN 0x80000
297#define DDR_FIX_TX_CMD_NEG_EDGE 0x00 141#define HOST_TO_DEVICE 0
298#define DDR_FIX_TX_CMD_14_AHEAD 0x20 142#define DEVICE_TO_HOST 1
299#define SD20_TX_NEG_EDGE 0x00
300#define SD20_TX_14_AHEAD 0x10
301#define SD20_TX_SEL_MASK 0x10
302#define DDR_VAR_SDCLK_POL_SWAP 0x01
303
304/* SD_TRANSFER */
305#define SD_TRANSFER_START 0x80
306#define SD_TRANSFER_END 0x40
307#define SD_STAT_IDLE 0x20
308#define SD_TRANSFER_ERR 0x10
309/* SD Transfer Mode definition */
310#define SD_TM_NORMAL_WRITE 0x00
311#define SD_TM_AUTO_WRITE_3 0x01
312#define SD_TM_AUTO_WRITE_4 0x02
313#define SD_TM_AUTO_READ_3 0x05
314#define SD_TM_AUTO_READ_4 0x06
315#define SD_TM_CMD_RSP 0x08
316#define SD_TM_AUTO_WRITE_1 0x09
317#define SD_TM_AUTO_WRITE_2 0x0A
318#define SD_TM_NORMAL_READ 0x0C
319#define SD_TM_AUTO_READ_1 0x0D
320#define SD_TM_AUTO_READ_2 0x0E
321#define SD_TM_AUTO_TUNING 0x0F
322
323/* SD_VPTX_CTL / SD_VPRX_CTL */
324#define PHASE_CHANGE 0x80
325#define PHASE_NOT_RESET 0x40
326
327/* SD_DCMPS_TX_CTL / SD_DCMPS_RX_CTL */
328#define DCMPS_CHANGE 0x80
329#define DCMPS_CHANGE_DONE 0x40
330#define DCMPS_ERROR 0x20
331#define DCMPS_CURRENT_PHASE 0x1F
332
333/* SD Configure 1 Register */
334#define SD_CLK_DIVIDE_0 0x00
335#define SD_CLK_DIVIDE_256 0xC0
336#define SD_CLK_DIVIDE_128 0x80
337#define SD_BUS_WIDTH_1BIT 0x00
338#define SD_BUS_WIDTH_4BIT 0x01
339#define SD_BUS_WIDTH_8BIT 0x02
340#define SD_ASYNC_FIFO_NOT_RST 0x10
341#define SD_20_MODE 0x00
342#define SD_DDR_MODE 0x04
343#define SD_30_MODE 0x08
344
345#define SD_CLK_DIVIDE_MASK 0xC0
346
347/* SD_CMD_STATE */
348#define SD_CMD_IDLE 0x80
349
350/* SD_DATA_STATE */
351#define SD_DATA_IDLE 0x80
352
353/* DCM_DRP_CTL */
354#define DCM_RESET 0x08
355#define DCM_LOCKED 0x04
356#define DCM_208M 0x00
357#define DCM_TX 0x01
358#define DCM_RX 0x02
359
360/* DCM_DRP_TRIG */
361#define DRP_START 0x80
362#define DRP_DONE 0x40
363
364/* DCM_DRP_CFG */
365#define DRP_WRITE 0x80
366#define DRP_READ 0x00
367#define DCM_WRITE_ADDRESS_50 0x50
368#define DCM_WRITE_ADDRESS_51 0x51
369#define DCM_READ_ADDRESS_00 0x00
370#define DCM_READ_ADDRESS_51 0x51
371
372/* IRQSTAT0 */
373#define DMA_DONE_INT 0x80
374#define SUSPEND_INT 0x40
375#define LINK_RDY_INT 0x20
376#define LINK_DOWN_INT 0x10
377
378/* DMACTL */
379#define DMA_RST 0x80
380#define DMA_BUSY 0x04
381#define DMA_DIR_TO_CARD 0x00
382#define DMA_DIR_FROM_CARD 0x02
383#define DMA_EN 0x01
384#define DMA_128 (0 << 4)
385#define DMA_256 (1 << 4)
386#define DMA_512 (2 << 4)
387#define DMA_1024 (3 << 4)
388#define DMA_PACK_SIZE_MASK 0x30
389
390/* SSC_CTL1 */
391#define SSC_RSTB 0x80
392#define SSC_8X_EN 0x40
393#define SSC_FIX_FRAC 0x20
394#define SSC_SEL_1M 0x00
395#define SSC_SEL_2M 0x08
396#define SSC_SEL_4M 0x10
397#define SSC_SEL_8M 0x18
398
399/* SSC_CTL2 */
400#define SSC_DEPTH_MASK 0x07
401#define SSC_DEPTH_DISALBE 0x00
402#define SSC_DEPTH_4M 0x01
403#define SSC_DEPTH_2M 0x02
404#define SSC_DEPTH_1M 0x03
405#define SSC_DEPTH_500K 0x04
406#define SSC_DEPTH_250K 0x05
407
408/* System Clock Control Register */
409#define CLK_LOW_FREQ 0x01
410
411/* System Clock Divider Register */
412#define CLK_DIV_1 0x01
413#define CLK_DIV_2 0x02
414#define CLK_DIV_4 0x03
415#define CLK_DIV_8 0x04
416
417/* MS_CFG */
418#define SAMPLE_TIME_RISING 0x00
419#define SAMPLE_TIME_FALLING 0x80
420#define PUSH_TIME_DEFAULT 0x00
421#define PUSH_TIME_ODD 0x40
422#define NO_EXTEND_TOGGLE 0x00
423#define EXTEND_TOGGLE_CHK 0x20
424#define MS_BUS_WIDTH_1 0x00
425#define MS_BUS_WIDTH_4 0x10
426#define MS_BUS_WIDTH_8 0x18
427#define MS_2K_SECTOR_MODE 0x04
428#define MS_512_SECTOR_MODE 0x00
429#define MS_TOGGLE_TIMEOUT_EN 0x00
430#define MS_TOGGLE_TIMEOUT_DISEN 0x01
431#define MS_NO_CHECK_INT 0x02
432 143
433/* MS_TRANS_CFG */ 144#define OUTPUT_3V3 0
434#define WAIT_INT 0x80 145#define OUTPUT_1V8 1
435#define NO_WAIT_INT 0x00 146
436#define NO_AUTO_READ_INT_REG 0x00 147#define RTSX_PHASE_MAX 32
437#define AUTO_READ_INT_REG 0x40 148#define RX_TUNING_CNT 3
438#define MS_CRC16_ERR 0x20
439#define MS_RDY_TIMEOUT 0x10
440#define MS_INT_CMDNK 0x08
441#define MS_INT_BREQ 0x04
442#define MS_INT_ERR 0x02
443#define MS_INT_CED 0x01
444
445/* MS_TRANSFER */
446#define MS_TRANSFER_START 0x80
447#define MS_TRANSFER_END 0x40
448#define MS_TRANSFER_ERR 0x20
449#define MS_BS_STATE 0x10
450#define MS_TM_READ_BYTES 0x00
451#define MS_TM_NORMAL_READ 0x01
452#define MS_TM_WRITE_BYTES 0x04
453#define MS_TM_NORMAL_WRITE 0x05
454#define MS_TM_AUTO_READ 0x08
455#define MS_TM_AUTO_WRITE 0x0C
456
457/* SD Configure 2 Register */
458#define SD_CALCULATE_CRC7 0x00
459#define SD_NO_CALCULATE_CRC7 0x80
460#define SD_CHECK_CRC16 0x00
461#define SD_NO_CHECK_CRC16 0x40
462#define SD_NO_CHECK_WAIT_CRC_TO 0x20
463#define SD_WAIT_BUSY_END 0x08
464#define SD_NO_WAIT_BUSY_END 0x00
465#define SD_CHECK_CRC7 0x00
466#define SD_NO_CHECK_CRC7 0x04
467#define SD_RSP_LEN_0 0x00
468#define SD_RSP_LEN_6 0x01
469#define SD_RSP_LEN_17 0x02
470/* SD/MMC Response Type Definition */
471#define SD_RSP_TYPE_R0 0x04
472#define SD_RSP_TYPE_R1 0x01
473#define SD_RSP_TYPE_R1b 0x09
474#define SD_RSP_TYPE_R2 0x02
475#define SD_RSP_TYPE_R3 0x05
476#define SD_RSP_TYPE_R4 0x05
477#define SD_RSP_TYPE_R5 0x01
478#define SD_RSP_TYPE_R6 0x01
479#define SD_RSP_TYPE_R7 0x01
480
481/* SD_CONFIGURE3 */
482#define SD_RSP_80CLK_TIMEOUT_EN 0x01
483
484/* Card Transfer Reset Register */
485#define SPI_STOP 0x01
486#define XD_STOP 0x02
487#define SD_STOP 0x04
488#define MS_STOP 0x08
489#define SPI_CLR_ERR 0x10
490#define XD_CLR_ERR 0x20
491#define SD_CLR_ERR 0x40
492#define MS_CLR_ERR 0x80
493
494/* Card Data Source Register */
495#define PINGPONG_BUFFER 0x01
496#define RING_BUFFER 0x00
497
498/* Card Power Control Register */
499#define PMOS_STRG_MASK 0x10
500#define PMOS_STRG_800mA 0x10
501#define PMOS_STRG_400mA 0x00
502#define SD_POWER_OFF 0x03
503#define SD_PARTIAL_POWER_ON 0x01
504#define SD_POWER_ON 0x00
505#define SD_POWER_MASK 0x03
506#define MS_POWER_OFF 0x0C
507#define MS_PARTIAL_POWER_ON 0x04
508#define MS_POWER_ON 0x00
509#define MS_POWER_MASK 0x0C
510#define BPP_POWER_OFF 0x0F
511#define BPP_POWER_5_PERCENT_ON 0x0E
512#define BPP_POWER_10_PERCENT_ON 0x0C
513#define BPP_POWER_15_PERCENT_ON 0x08
514#define BPP_POWER_ON 0x00
515#define BPP_POWER_MASK 0x0F
516#define SD_VCC_PARTIAL_POWER_ON 0x02
517#define SD_VCC_POWER_ON 0x00
518
519/* PWR_GATE_CTRL */
520#define PWR_GATE_EN 0x01
521#define LDO3318_PWR_MASK 0x06
522#define LDO_ON 0x00
523#define LDO_SUSPEND 0x04
524#define LDO_OFF 0x06
525
526/* CARD_CLK_SOURCE */
527#define CRC_FIX_CLK (0x00 << 0)
528#define CRC_VAR_CLK0 (0x01 << 0)
529#define CRC_VAR_CLK1 (0x02 << 0)
530#define SD30_FIX_CLK (0x00 << 2)
531#define SD30_VAR_CLK0 (0x01 << 2)
532#define SD30_VAR_CLK1 (0x02 << 2)
533#define SAMPLE_FIX_CLK (0x00 << 4)
534#define SAMPLE_VAR_CLK0 (0x01 << 4)
535#define SAMPLE_VAR_CLK1 (0x02 << 4)
536
537/* HOST_SLEEP_STATE */
538#define HOST_ENTER_S1 1
539#define HOST_ENTER_S3 2
540 149
541#define MS_CFG 0xFD40 150#define MS_CFG 0xFD40
151#define SAMPLE_TIME_RISING 0x00
152#define SAMPLE_TIME_FALLING 0x80
153#define PUSH_TIME_DEFAULT 0x00
154#define PUSH_TIME_ODD 0x40
155#define NO_EXTEND_TOGGLE 0x00
156#define EXTEND_TOGGLE_CHK 0x20
157#define MS_BUS_WIDTH_1 0x00
158#define MS_BUS_WIDTH_4 0x10
159#define MS_BUS_WIDTH_8 0x18
160#define MS_2K_SECTOR_MODE 0x04
161#define MS_512_SECTOR_MODE 0x00
162#define MS_TOGGLE_TIMEOUT_EN 0x00
163#define MS_TOGGLE_TIMEOUT_DISEN 0x01
164#define MS_NO_CHECK_INT 0x02
542#define MS_TPC 0xFD41 165#define MS_TPC 0xFD41
543#define MS_TRANS_CFG 0xFD42 166#define MS_TRANS_CFG 0xFD42
167#define WAIT_INT 0x80
168#define NO_WAIT_INT 0x00
169#define NO_AUTO_READ_INT_REG 0x00
170#define AUTO_READ_INT_REG 0x40
171#define MS_CRC16_ERR 0x20
172#define MS_RDY_TIMEOUT 0x10
173#define MS_INT_CMDNK 0x08
174#define MS_INT_BREQ 0x04
175#define MS_INT_ERR 0x02
176#define MS_INT_CED 0x01
544#define MS_TRANSFER 0xFD43 177#define MS_TRANSFER 0xFD43
178#define MS_TRANSFER_START 0x80
179#define MS_TRANSFER_END 0x40
180#define MS_TRANSFER_ERR 0x20
181#define MS_BS_STATE 0x10
182#define MS_TM_READ_BYTES 0x00
183#define MS_TM_NORMAL_READ 0x01
184#define MS_TM_WRITE_BYTES 0x04
185#define MS_TM_NORMAL_WRITE 0x05
186#define MS_TM_AUTO_READ 0x08
187#define MS_TM_AUTO_WRITE 0x0C
545#define MS_INT_REG 0xFD44 188#define MS_INT_REG 0xFD44
546#define MS_BYTE_CNT 0xFD45 189#define MS_BYTE_CNT 0xFD45
547#define MS_SECTOR_CNT_L 0xFD46 190#define MS_SECTOR_CNT_L 0xFD46
@@ -549,14 +192,90 @@
549#define MS_DBUS_H 0xFD48 192#define MS_DBUS_H 0xFD48
550 193
551#define SD_CFG1 0xFDA0 194#define SD_CFG1 0xFDA0
195#define SD_CLK_DIVIDE_0 0x00
196#define SD_CLK_DIVIDE_256 0xC0
197#define SD_CLK_DIVIDE_128 0x80
198#define SD_BUS_WIDTH_1BIT 0x00
199#define SD_BUS_WIDTH_4BIT 0x01
200#define SD_BUS_WIDTH_8BIT 0x02
201#define SD_ASYNC_FIFO_NOT_RST 0x10
202#define SD_20_MODE 0x00
203#define SD_DDR_MODE 0x04
204#define SD_30_MODE 0x08
205#define SD_CLK_DIVIDE_MASK 0xC0
552#define SD_CFG2 0xFDA1 206#define SD_CFG2 0xFDA1
207#define SD_CALCULATE_CRC7 0x00
208#define SD_NO_CALCULATE_CRC7 0x80
209#define SD_CHECK_CRC16 0x00
210#define SD_NO_CHECK_CRC16 0x40
211#define SD_NO_CHECK_WAIT_CRC_TO 0x20
212#define SD_WAIT_BUSY_END 0x08
213#define SD_NO_WAIT_BUSY_END 0x00
214#define SD_CHECK_CRC7 0x00
215#define SD_NO_CHECK_CRC7 0x04
216#define SD_RSP_LEN_0 0x00
217#define SD_RSP_LEN_6 0x01
218#define SD_RSP_LEN_17 0x02
219#define SD_RSP_TYPE_R0 0x04
220#define SD_RSP_TYPE_R1 0x01
221#define SD_RSP_TYPE_R1b 0x09
222#define SD_RSP_TYPE_R2 0x02
223#define SD_RSP_TYPE_R3 0x05
224#define SD_RSP_TYPE_R4 0x05
225#define SD_RSP_TYPE_R5 0x01
226#define SD_RSP_TYPE_R6 0x01
227#define SD_RSP_TYPE_R7 0x01
553#define SD_CFG3 0xFDA2 228#define SD_CFG3 0xFDA2
229#define SD_RSP_80CLK_TIMEOUT_EN 0x01
230
554#define SD_STAT1 0xFDA3 231#define SD_STAT1 0xFDA3
232#define SD_CRC7_ERR 0x80
233#define SD_CRC16_ERR 0x40
234#define SD_CRC_WRITE_ERR 0x20
235#define SD_CRC_WRITE_ERR_MASK 0x1C
236#define GET_CRC_TIME_OUT 0x02
237#define SD_TUNING_COMPARE_ERR 0x01
555#define SD_STAT2 0xFDA4 238#define SD_STAT2 0xFDA4
239#define SD_RSP_80CLK_TIMEOUT 0x01
240
556#define SD_BUS_STAT 0xFDA5 241#define SD_BUS_STAT 0xFDA5
242#define SD_CLK_TOGGLE_EN 0x80
243#define SD_CLK_FORCE_STOP 0x40
244#define SD_DAT3_STATUS 0x10
245#define SD_DAT2_STATUS 0x08
246#define SD_DAT1_STATUS 0x04
247#define SD_DAT0_STATUS 0x02
248#define SD_CMD_STATUS 0x01
557#define SD_PAD_CTL 0xFDA6 249#define SD_PAD_CTL 0xFDA6
250#define SD_IO_USING_1V8 0x80
251#define SD_IO_USING_3V3 0x7F
252#define TYPE_A_DRIVING 0x00
253#define TYPE_B_DRIVING 0x01
254#define TYPE_C_DRIVING 0x02
255#define TYPE_D_DRIVING 0x03
558#define SD_SAMPLE_POINT_CTL 0xFDA7 256#define SD_SAMPLE_POINT_CTL 0xFDA7
257#define DDR_FIX_RX_DAT 0x00
258#define DDR_VAR_RX_DAT 0x80
259#define DDR_FIX_RX_DAT_EDGE 0x00
260#define DDR_FIX_RX_DAT_14_DELAY 0x40
261#define DDR_FIX_RX_CMD 0x00
262#define DDR_VAR_RX_CMD 0x20
263#define DDR_FIX_RX_CMD_POS_EDGE 0x00
264#define DDR_FIX_RX_CMD_14_DELAY 0x10
265#define SD20_RX_POS_EDGE 0x00
266#define SD20_RX_14_DELAY 0x08
267#define SD20_RX_SEL_MASK 0x08
559#define SD_PUSH_POINT_CTL 0xFDA8 268#define SD_PUSH_POINT_CTL 0xFDA8
269#define DDR_FIX_TX_CMD_DAT 0x00
270#define DDR_VAR_TX_CMD_DAT 0x80
271#define DDR_FIX_TX_DAT_14_TSU 0x00
272#define DDR_FIX_TX_DAT_12_TSU 0x40
273#define DDR_FIX_TX_CMD_NEG_EDGE 0x00
274#define DDR_FIX_TX_CMD_14_AHEAD 0x20
275#define SD20_TX_NEG_EDGE 0x00
276#define SD20_TX_14_AHEAD 0x10
277#define SD20_TX_SEL_MASK 0x10
278#define DDR_VAR_SDCLK_POL_SWAP 0x01
560#define SD_CMD0 0xFDA9 279#define SD_CMD0 0xFDA9
561#define SD_CMD_START 0x40 280#define SD_CMD_START 0x40
562#define SD_CMD1 0xFDAA 281#define SD_CMD1 0xFDAA
@@ -569,60 +288,203 @@
569#define SD_BLOCK_CNT_L 0xFDB1 288#define SD_BLOCK_CNT_L 0xFDB1
570#define SD_BLOCK_CNT_H 0xFDB2 289#define SD_BLOCK_CNT_H 0xFDB2
571#define SD_TRANSFER 0xFDB3 290#define SD_TRANSFER 0xFDB3
291#define SD_TRANSFER_START 0x80
292#define SD_TRANSFER_END 0x40
293#define SD_STAT_IDLE 0x20
294#define SD_TRANSFER_ERR 0x10
295#define SD_TM_NORMAL_WRITE 0x00
296#define SD_TM_AUTO_WRITE_3 0x01
297#define SD_TM_AUTO_WRITE_4 0x02
298#define SD_TM_AUTO_READ_3 0x05
299#define SD_TM_AUTO_READ_4 0x06
300#define SD_TM_CMD_RSP 0x08
301#define SD_TM_AUTO_WRITE_1 0x09
302#define SD_TM_AUTO_WRITE_2 0x0A
303#define SD_TM_NORMAL_READ 0x0C
304#define SD_TM_AUTO_READ_1 0x0D
305#define SD_TM_AUTO_READ_2 0x0E
306#define SD_TM_AUTO_TUNING 0x0F
572#define SD_CMD_STATE 0xFDB5 307#define SD_CMD_STATE 0xFDB5
308#define SD_CMD_IDLE 0x80
309
573#define SD_DATA_STATE 0xFDB6 310#define SD_DATA_STATE 0xFDB6
311#define SD_DATA_IDLE 0x80
574 312
575#define SRCTL 0xFC13 313#define SRCTL 0xFC13
576 314
577#define DCM_DRP_CTL 0xFC23 315#define DCM_DRP_CTL 0xFC23
578#define DCM_DRP_TRIG 0xFC24 316#define DCM_RESET 0x08
579#define DCM_DRP_CFG 0xFC25 317#define DCM_LOCKED 0x04
580#define DCM_DRP_WR_DATA_L 0xFC26 318#define DCM_208M 0x00
581#define DCM_DRP_WR_DATA_H 0xFC27 319#define DCM_TX 0x01
582#define DCM_DRP_RD_DATA_L 0xFC28 320#define DCM_RX 0x02
583#define DCM_DRP_RD_DATA_H 0xFC29 321#define DCM_DRP_TRIG 0xFC24
322#define DRP_START 0x80
323#define DRP_DONE 0x40
324#define DCM_DRP_CFG 0xFC25
325#define DRP_WRITE 0x80
326#define DRP_READ 0x00
327#define DCM_WRITE_ADDRESS_50 0x50
328#define DCM_WRITE_ADDRESS_51 0x51
329#define DCM_READ_ADDRESS_00 0x00
330#define DCM_READ_ADDRESS_51 0x51
331#define DCM_DRP_WR_DATA_L 0xFC26
332#define DCM_DRP_WR_DATA_H 0xFC27
333#define DCM_DRP_RD_DATA_L 0xFC28
334#define DCM_DRP_RD_DATA_H 0xFC29
584#define SD_VPCLK0_CTL 0xFC2A 335#define SD_VPCLK0_CTL 0xFC2A
585#define SD_VPCLK1_CTL 0xFC2B 336#define SD_VPCLK1_CTL 0xFC2B
586#define SD_DCMPS0_CTL 0xFC2C 337#define SD_DCMPS0_CTL 0xFC2C
587#define SD_DCMPS1_CTL 0xFC2D 338#define SD_DCMPS1_CTL 0xFC2D
588#define SD_VPTX_CTL SD_VPCLK0_CTL 339#define SD_VPTX_CTL SD_VPCLK0_CTL
589#define SD_VPRX_CTL SD_VPCLK1_CTL 340#define SD_VPRX_CTL SD_VPCLK1_CTL
341#define PHASE_CHANGE 0x80
342#define PHASE_NOT_RESET 0x40
590#define SD_DCMPS_TX_CTL SD_DCMPS0_CTL 343#define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
591#define SD_DCMPS_RX_CTL SD_DCMPS1_CTL 344#define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
345#define DCMPS_CHANGE 0x80
346#define DCMPS_CHANGE_DONE 0x40
347#define DCMPS_ERROR 0x20
348#define DCMPS_CURRENT_PHASE 0x1F
592#define CARD_CLK_SOURCE 0xFC2E 349#define CARD_CLK_SOURCE 0xFC2E
593 350#define CRC_FIX_CLK (0x00 << 0)
351#define CRC_VAR_CLK0 (0x01 << 0)
352#define CRC_VAR_CLK1 (0x02 << 0)
353#define SD30_FIX_CLK (0x00 << 2)
354#define SD30_VAR_CLK0 (0x01 << 2)
355#define SD30_VAR_CLK1 (0x02 << 2)
356#define SAMPLE_FIX_CLK (0x00 << 4)
357#define SAMPLE_VAR_CLK0 (0x01 << 4)
358#define SAMPLE_VAR_CLK1 (0x02 << 4)
594#define CARD_PWR_CTL 0xFD50 359#define CARD_PWR_CTL 0xFD50
360#define PMOS_STRG_MASK 0x10
361#define PMOS_STRG_800mA 0x10
362#define PMOS_STRG_400mA 0x00
363#define SD_POWER_OFF 0x03
364#define SD_PARTIAL_POWER_ON 0x01
365#define SD_POWER_ON 0x00
366#define SD_POWER_MASK 0x03
367#define MS_POWER_OFF 0x0C
368#define MS_PARTIAL_POWER_ON 0x04
369#define MS_POWER_ON 0x00
370#define MS_POWER_MASK 0x0C
371#define BPP_POWER_OFF 0x0F
372#define BPP_POWER_5_PERCENT_ON 0x0E
373#define BPP_POWER_10_PERCENT_ON 0x0C
374#define BPP_POWER_15_PERCENT_ON 0x08
375#define BPP_POWER_ON 0x00
376#define BPP_POWER_MASK 0x0F
377#define SD_VCC_PARTIAL_POWER_ON 0x02
378#define SD_VCC_POWER_ON 0x00
595#define CARD_CLK_SWITCH 0xFD51 379#define CARD_CLK_SWITCH 0xFD51
596#define RTL8411B_PACKAGE_MODE 0xFD51 380#define RTL8411B_PACKAGE_MODE 0xFD51
597#define CARD_SHARE_MODE 0xFD52 381#define CARD_SHARE_MODE 0xFD52
382#define CARD_SHARE_MASK 0x0F
383#define CARD_SHARE_MULTI_LUN 0x00
384#define CARD_SHARE_NORMAL 0x00
385#define CARD_SHARE_48_SD 0x04
386#define CARD_SHARE_48_MS 0x08
387#define CARD_SHARE_BAROSSA_SD 0x01
388#define CARD_SHARE_BAROSSA_MS 0x02
598#define CARD_DRIVE_SEL 0xFD53 389#define CARD_DRIVE_SEL 0xFD53
390#define MS_DRIVE_8mA (0x01 << 6)
391#define MMC_DRIVE_8mA (0x01 << 4)
392#define XD_DRIVE_8mA (0x01 << 2)
393#define GPIO_DRIVE_8mA 0x01
394#define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
395 XD_DRIVE_8mA | GPIO_DRIVE_8mA)
396#define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
397 XD_DRIVE_8mA)
398#define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA)
399
599#define CARD_STOP 0xFD54 400#define CARD_STOP 0xFD54
401#define SPI_STOP 0x01
402#define XD_STOP 0x02
403#define SD_STOP 0x04
404#define MS_STOP 0x08
405#define SPI_CLR_ERR 0x10
406#define XD_CLR_ERR 0x20
407#define SD_CLR_ERR 0x40
408#define MS_CLR_ERR 0x80
600#define CARD_OE 0xFD55 409#define CARD_OE 0xFD55
410#define SD_OUTPUT_EN 0x04
411#define MS_OUTPUT_EN 0x08
601#define CARD_AUTO_BLINK 0xFD56 412#define CARD_AUTO_BLINK 0xFD56
602#define CARD_GPIO_DIR 0xFD57 413#define CARD_GPIO_DIR 0xFD57
603#define CARD_GPIO 0xFD58 414#define CARD_GPIO 0xFD58
604#define CARD_DATA_SOURCE 0xFD5B 415#define CARD_DATA_SOURCE 0xFD5B
416#define PINGPONG_BUFFER 0x01
417#define RING_BUFFER 0x00
605#define SD30_CLK_DRIVE_SEL 0xFD5A 418#define SD30_CLK_DRIVE_SEL 0xFD5A
419#define DRIVER_TYPE_A 0x05
420#define DRIVER_TYPE_B 0x03
421#define DRIVER_TYPE_C 0x02
422#define DRIVER_TYPE_D 0x01
606#define CARD_SELECT 0xFD5C 423#define CARD_SELECT 0xFD5C
424#define SD_MOD_SEL 2
425#define MS_MOD_SEL 3
607#define SD30_DRIVE_SEL 0xFD5E 426#define SD30_DRIVE_SEL 0xFD5E
427#define CFG_DRIVER_TYPE_A 0x02
428#define CFG_DRIVER_TYPE_B 0x03
429#define CFG_DRIVER_TYPE_C 0x01
430#define CFG_DRIVER_TYPE_D 0x00
608#define SD30_CMD_DRIVE_SEL 0xFD5E 431#define SD30_CMD_DRIVE_SEL 0xFD5E
609#define SD30_DAT_DRIVE_SEL 0xFD5F 432#define SD30_DAT_DRIVE_SEL 0xFD5F
610#define CARD_CLK_EN 0xFD69 433#define CARD_CLK_EN 0xFD69
434#define SD_CLK_EN 0x04
435#define MS_CLK_EN 0x08
611#define SDIO_CTRL 0xFD6B 436#define SDIO_CTRL 0xFD6B
612#define CD_PAD_CTL 0xFD73 437#define CD_PAD_CTL 0xFD73
613 438#define CD_DISABLE_MASK 0x07
439#define MS_CD_DISABLE 0x04
440#define SD_CD_DISABLE 0x02
441#define XD_CD_DISABLE 0x01
442#define CD_DISABLE 0x07
443#define CD_ENABLE 0x00
444#define MS_CD_EN_ONLY 0x03
445#define SD_CD_EN_ONLY 0x05
446#define XD_CD_EN_ONLY 0x06
447#define FORCE_CD_LOW_MASK 0x38
448#define FORCE_CD_XD_LOW 0x08
449#define FORCE_CD_SD_LOW 0x10
450#define FORCE_CD_MS_LOW 0x20
451#define CD_AUTO_DISABLE 0x40
614#define FPDCTL 0xFC00 452#define FPDCTL 0xFC00
453#define SSC_POWER_DOWN 0x01
454#define SD_OC_POWER_DOWN 0x02
455#define ALL_POWER_DOWN 0x07
456#define OC_POWER_DOWN 0x06
615#define PDINFO 0xFC01 457#define PDINFO 0xFC01
616 458
617#define CLK_CTL 0xFC02 459#define CLK_CTL 0xFC02
460#define CHANGE_CLK 0x01
461#define CLK_LOW_FREQ 0x01
462
618#define CLK_DIV 0xFC03 463#define CLK_DIV 0xFC03
464#define CLK_DIV_1 0x01
465#define CLK_DIV_2 0x02
466#define CLK_DIV_4 0x03
467#define CLK_DIV_8 0x04
619#define CLK_SEL 0xFC04 468#define CLK_SEL 0xFC04
620 469
621#define SSC_DIV_N_0 0xFC0F 470#define SSC_DIV_N_0 0xFC0F
622#define SSC_DIV_N_1 0xFC10 471#define SSC_DIV_N_1 0xFC10
623#define SSC_CTL1 0xFC11 472#define SSC_CTL1 0xFC11
473#define SSC_RSTB 0x80
474#define SSC_8X_EN 0x40
475#define SSC_FIX_FRAC 0x20
476#define SSC_SEL_1M 0x00
477#define SSC_SEL_2M 0x08
478#define SSC_SEL_4M 0x10
479#define SSC_SEL_8M 0x18
624#define SSC_CTL2 0xFC12 480#define SSC_CTL2 0xFC12
625 481#define SSC_DEPTH_MASK 0x07
482#define SSC_DEPTH_DISALBE 0x00
483#define SSC_DEPTH_4M 0x01
484#define SSC_DEPTH_2M 0x02
485#define SSC_DEPTH_1M 0x03
486#define SSC_DEPTH_500K 0x04
487#define SSC_DEPTH_250K 0x05
626#define RCCTL 0xFC14 488#define RCCTL 0xFC14
627 489
628#define FPGA_PULL_CTL 0xFC1D 490#define FPGA_PULL_CTL 0xFC1D
@@ -630,6 +492,24 @@
630#define GPIO_CTL 0xFC1F 492#define GPIO_CTL 0xFC1F
631 493
632#define LDO_CTL 0xFC1E 494#define LDO_CTL 0xFC1E
495#define BPP_ASIC_1V7 0x00
496#define BPP_ASIC_1V8 0x01
497#define BPP_ASIC_1V9 0x02
498#define BPP_ASIC_2V0 0x03
499#define BPP_ASIC_2V7 0x04
500#define BPP_ASIC_2V8 0x05
501#define BPP_ASIC_3V2 0x06
502#define BPP_ASIC_3V3 0x07
503#define BPP_REG_TUNED18 0x07
504#define BPP_TUNED18_SHIFT_8402 5
505#define BPP_TUNED18_SHIFT_8411 4
506#define BPP_PAD_MASK 0x04
507#define BPP_PAD_3V3 0x04
508#define BPP_PAD_1V8 0x00
509#define BPP_LDO_POWB 0x03
510#define BPP_LDO_ON 0x00
511#define BPP_LDO_SUSPEND 0x02
512#define BPP_LDO_OFF 0x03
633#define SYS_VER 0xFC32 513#define SYS_VER 0xFC32
634 514
635#define CARD_PULL_CTL1 0xFD60 515#define CARD_PULL_CTL1 0xFD60
@@ -642,6 +522,10 @@
642/* PCI Express Related Registers */ 522/* PCI Express Related Registers */
643#define IRQEN0 0xFE20 523#define IRQEN0 0xFE20
644#define IRQSTAT0 0xFE21 524#define IRQSTAT0 0xFE21
525#define DMA_DONE_INT 0x80
526#define SUSPEND_INT 0x40
527#define LINK_RDY_INT 0x20
528#define LINK_DOWN_INT 0x10
645#define IRQEN1 0xFE22 529#define IRQEN1 0xFE22
646#define IRQSTAT1 0xFE23 530#define IRQSTAT1 0xFE23
647#define TLPRIEN 0xFE24 531#define TLPRIEN 0xFE24
@@ -653,6 +537,16 @@
653#define DMATC2 0xFE2A 537#define DMATC2 0xFE2A
654#define DMATC3 0xFE2B 538#define DMATC3 0xFE2B
655#define DMACTL 0xFE2C 539#define DMACTL 0xFE2C
540#define DMA_RST 0x80
541#define DMA_BUSY 0x04
542#define DMA_DIR_TO_CARD 0x00
543#define DMA_DIR_FROM_CARD 0x02
544#define DMA_EN 0x01
545#define DMA_128 (0 << 4)
546#define DMA_256 (1 << 4)
547#define DMA_512 (2 << 4)
548#define DMA_1024 (3 << 4)
549#define DMA_PACK_SIZE_MASK 0x30
656#define BCTL 0xFE2D 550#define BCTL 0xFE2D
657#define RBBC0 0xFE2E 551#define RBBC0 0xFE2E
658#define RBBC1 0xFE2F 552#define RBBC1 0xFE2F
@@ -678,14 +572,21 @@
678#define MSGTXDATA2 0xFE46 572#define MSGTXDATA2 0xFE46
679#define MSGTXDATA3 0xFE47 573#define MSGTXDATA3 0xFE47
680#define MSGTXCTL 0xFE48 574#define MSGTXCTL 0xFE48
681#define PETXCFG 0xFE49
682#define LTR_CTL 0xFE4A 575#define LTR_CTL 0xFE4A
683#define OBFF_CFG 0xFE4C 576#define OBFF_CFG 0xFE4C
684 577
685#define CDRESUMECTL 0xFE52 578#define CDRESUMECTL 0xFE52
686#define WAKE_SEL_CTL 0xFE54 579#define WAKE_SEL_CTL 0xFE54
580#define PCLK_CTL 0xFE55
581#define PCLK_MODE_SEL 0x20
687#define PME_FORCE_CTL 0xFE56 582#define PME_FORCE_CTL 0xFE56
583
688#define ASPM_FORCE_CTL 0xFE57 584#define ASPM_FORCE_CTL 0xFE57
585#define FORCE_ASPM_CTL0 0x10
586#define FORCE_ASPM_VAL_MASK 0x03
587#define FORCE_ASPM_L1_EN 0x02
588#define FORCE_ASPM_L0_EN 0x01
589#define FORCE_ASPM_NO_ASPM 0x00
689#define PM_CLK_FORCE_CTL 0xFE58 590#define PM_CLK_FORCE_CTL 0xFE58
690#define FUNC_FORCE_CTL 0xFE59 591#define FUNC_FORCE_CTL 0xFE59
691#define PERST_GLITCH_WIDTH 0xFE5C 592#define PERST_GLITCH_WIDTH 0xFE5C
@@ -693,19 +594,36 @@
693#define RESET_LOAD_REG 0xFE5E 594#define RESET_LOAD_REG 0xFE5E
694#define EFUSE_CONTENT 0xFE5F 595#define EFUSE_CONTENT 0xFE5F
695#define HOST_SLEEP_STATE 0xFE60 596#define HOST_SLEEP_STATE 0xFE60
696#define SDIO_CFG 0xFE70 597#define HOST_ENTER_S1 1
598#define HOST_ENTER_S3 2
697 599
600#define SDIO_CFG 0xFE70
601#define PM_EVENT_DEBUG 0xFE71
602#define PME_DEBUG_0 0x08
698#define NFTS_TX_CTRL 0xFE72 603#define NFTS_TX_CTRL 0xFE72
699 604
700#define PWR_GATE_CTRL 0xFE75 605#define PWR_GATE_CTRL 0xFE75
606#define PWR_GATE_EN 0x01
607#define LDO3318_PWR_MASK 0x06
608#define LDO_ON 0x00
609#define LDO_SUSPEND 0x04
610#define LDO_OFF 0x06
701#define PWD_SUSPEND_EN 0xFE76 611#define PWD_SUSPEND_EN 0xFE76
702#define LDO_PWR_SEL 0xFE78 612#define LDO_PWR_SEL 0xFE78
703 613
614#define L1SUB_CONFIG1 0xFE8D
615#define L1SUB_CONFIG2 0xFE8E
616#define L1SUB_AUTO_CFG 0x02
617#define L1SUB_CONFIG3 0xFE8F
618
704#define DUMMY_REG_RESET_0 0xFE90 619#define DUMMY_REG_RESET_0 0xFE90
705 620
706#define AUTOLOAD_CFG_BASE 0xFF00 621#define AUTOLOAD_CFG_BASE 0xFF00
622#define PETXCFG 0xFF03
707 623
708#define PM_CTRL1 0xFF44 624#define PM_CTRL1 0xFF44
625#define CD_RESUME_EN_MASK 0xF0
626
709#define PM_CTRL2 0xFF45 627#define PM_CTRL2 0xFF45
710#define PM_CTRL3 0xFF46 628#define PM_CTRL3 0xFF46
711#define SDIO_SEND_PME_EN 0x80 629#define SDIO_SEND_PME_EN 0x80
@@ -726,18 +644,125 @@
726#define IMAGE_FLAG_ADDR0 0xCE80 644#define IMAGE_FLAG_ADDR0 0xCE80
727#define IMAGE_FLAG_ADDR1 0xCE81 645#define IMAGE_FLAG_ADDR1 0xCE81
728 646
647#define RREF_CFG 0xFF6C
648#define RREF_VBGSEL_MASK 0x38
649#define RREF_VBGSEL_1V25 0x28
650
651#define OOBS_CONFIG 0xFF6E
652#define OOBS_AUTOK_DIS 0x80
653#define OOBS_VAL_MASK 0x1F
654
655#define LDO_DV18_CFG 0xFF70
656#define LDO_DV18_SR_MASK 0xC0
657#define LDO_DV18_SR_DF 0x40
658
659#define LDO_CONFIG2 0xFF71
660#define LDO_D3318_MASK 0x07
661#define LDO_D3318_33V 0x07
662#define LDO_D3318_18V 0x02
663
664#define LDO_VCC_CFG0 0xFF72
665#define LDO_VCC_LMTVTH_MASK 0x30
666#define LDO_VCC_LMTVTH_2A 0x10
667
668#define LDO_VCC_CFG1 0xFF73
669#define LDO_VCC_REF_TUNE_MASK 0x30
670#define LDO_VCC_REF_1V2 0x20
671#define LDO_VCC_TUNE_MASK 0x07
672#define LDO_VCC_1V8 0x04
673#define LDO_VCC_3V3 0x07
674#define LDO_VCC_LMT_EN 0x08
675
676#define LDO_VIO_CFG 0xFF75
677#define LDO_VIO_SR_MASK 0xC0
678#define LDO_VIO_SR_DF 0x40
679#define LDO_VIO_REF_TUNE_MASK 0x30
680#define LDO_VIO_REF_1V2 0x20
681#define LDO_VIO_TUNE_MASK 0x07
682#define LDO_VIO_1V7 0x03
683#define LDO_VIO_1V8 0x04
684#define LDO_VIO_3V3 0x07
685
686#define LDO_DV12S_CFG 0xFF76
687#define LDO_REF12_TUNE_MASK 0x18
688#define LDO_REF12_TUNE_DF 0x10
689#define LDO_D12_TUNE_MASK 0x07
690#define LDO_D12_TUNE_DF 0x04
691
692#define LDO_AV12S_CFG 0xFF77
693#define LDO_AV12S_TUNE_MASK 0x07
694#define LDO_AV12S_TUNE_DF 0x04
695
696#define SD40_LDO_CTL1 0xFE7D
697#define SD40_VIO_TUNE_MASK 0x70
698#define SD40_VIO_TUNE_1V7 0x30
699#define SD_VIO_LDO_1V8 0x40
700#define SD_VIO_LDO_3V3 0x70
701
729/* Phy register */ 702/* Phy register */
730#define PHY_PCR 0x00 703#define PHY_PCR 0x00
704#define PHY_PCR_FORCE_CODE 0xB000
705#define PHY_PCR_OOBS_CALI_50 0x0800
706#define PHY_PCR_OOBS_VCM_08 0x0200
707#define PHY_PCR_OOBS_SEN_90 0x0040
708#define PHY_PCR_RSSI_EN 0x0002
709#define PHY_PCR_RX10K 0x0001
710
731#define PHY_RCR0 0x01 711#define PHY_RCR0 0x01
732#define PHY_RCR1 0x02 712#define PHY_RCR1 0x02
713#define PHY_RCR1_ADP_TIME_4 0x0400
714#define PHY_RCR1_VCO_COARSE 0x001F
715#define PHY_SSCCR2 0x02
716#define PHY_SSCCR2_PLL_NCODE 0x0A00
717#define PHY_SSCCR2_TIME0 0x001C
718#define PHY_SSCCR2_TIME2_WIDTH 0x0003
719
733#define PHY_RCR2 0x03 720#define PHY_RCR2 0x03
721#define PHY_RCR2_EMPHASE_EN 0x8000
722#define PHY_RCR2_NADJR 0x4000
723#define PHY_RCR2_CDR_SR_2 0x0100
724#define PHY_RCR2_FREQSEL_12 0x0040
725#define PHY_RCR2_CDR_SC_12P 0x0010
726#define PHY_RCR2_CALIB_LATE 0x0002
727#define PHY_SSCCR3 0x03
728#define PHY_SSCCR3_STEP_IN 0x2740
729#define PHY_SSCCR3_CHECK_DELAY 0x0008
730#define _PHY_ANA03 0x03
731#define _PHY_ANA03_TIMER_MAX 0x2700
732#define _PHY_ANA03_OOBS_DEB_EN 0x0040
733#define _PHY_CMU_DEBUG_EN 0x0008
734
734#define PHY_RTCR 0x04 735#define PHY_RTCR 0x04
735#define PHY_RDR 0x05 736#define PHY_RDR 0x05
737#define PHY_RDR_RXDSEL_1_9 0x4000
738#define PHY_SSC_AUTO_PWD 0x0600
736#define PHY_TCR0 0x06 739#define PHY_TCR0 0x06
737#define PHY_TCR1 0x07 740#define PHY_TCR1 0x07
738#define PHY_TUNE 0x08 741#define PHY_TUNE 0x08
742#define PHY_TUNE_TUNEREF_1_0 0x4000
743#define PHY_TUNE_VBGSEL_1252 0x0C00
744#define PHY_TUNE_SDBUS_33 0x0200
745#define PHY_TUNE_TUNED18 0x01C0
746#define PHY_TUNE_TUNED12 0X0020
747#define PHY_TUNE_TUNEA12 0x0004
748#define PHY_TUNE_VOLTAGE_MASK 0xFC3F
749#define PHY_TUNE_VOLTAGE_3V3 0x03C0
750#define PHY_TUNE_D18_1V8 0x0100
751#define PHY_TUNE_D18_1V7 0x0080
752#define PHY_ANA08 0x08
753#define PHY_ANA08_RX_EQ_DCGAIN 0x5000
754#define PHY_ANA08_SEL_RX_EN 0x0400
755#define PHY_ANA08_RX_EQ_VAL 0x03C0
756#define PHY_ANA08_SCP 0x0020
757#define PHY_ANA08_SEL_IPI 0x0004
758
739#define PHY_IMR 0x09 759#define PHY_IMR 0x09
740#define PHY_BPCR 0x0A 760#define PHY_BPCR 0x0A
761#define PHY_BPCR_IBRXSEL 0x0400
762#define PHY_BPCR_IBTXSEL 0x0100
763#define PHY_BPCR_IB_FILTER 0x0080
764#define PHY_BPCR_CMIRROR_EN 0x0040
765
741#define PHY_BIST 0x0B 766#define PHY_BIST 0x0B
742#define PHY_RAW_L 0x0C 767#define PHY_RAW_L 0x0C
743#define PHY_RAW_H 0x0D 768#define PHY_RAW_H 0x0D
@@ -745,6 +770,7 @@
745#define PHY_HOST_CLK_CTRL 0x0F 770#define PHY_HOST_CLK_CTRL 0x0F
746#define PHY_DMR 0x10 771#define PHY_DMR 0x10
747#define PHY_BACR 0x11 772#define PHY_BACR 0x11
773#define PHY_BACR_BASIC_MASK 0xFFF3
748#define PHY_IER 0x12 774#define PHY_IER 0x12
749#define PHY_BCSR 0x13 775#define PHY_BCSR 0x13
750#define PHY_BPR 0x14 776#define PHY_BPR 0x14
@@ -752,80 +778,70 @@
752#define PHY_BPNR 0x16 778#define PHY_BPNR 0x16
753#define PHY_BRNR2 0x17 779#define PHY_BRNR2 0x17
754#define PHY_BENR 0x18 780#define PHY_BENR 0x18
755#define PHY_REG_REV 0x19 781#define PHY_REV 0x19
782#define PHY_REV_RESV 0xE000
783#define PHY_REV_RXIDLE_LATCHED 0x1000
784#define PHY_REV_P1_EN 0x0800
785#define PHY_REV_RXIDLE_EN 0x0400
786#define PHY_REV_CLKREQ_TX_EN 0x0200
787#define PHY_REV_CLKREQ_RX_EN 0x0100
788#define PHY_REV_CLKREQ_DT_1_0 0x0040
789#define PHY_REV_STOP_CLKRD 0x0020
790#define PHY_REV_RX_PWST 0x0008
791#define PHY_REV_STOP_CLKWR 0x0004
792#define _PHY_REV0 0x19
793#define _PHY_REV0_FILTER_OUT 0x3800
794#define _PHY_REV0_CDR_BYPASS_PFD 0x0100
795#define _PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002
796
756#define PHY_FLD0 0x1A 797#define PHY_FLD0 0x1A
798#define PHY_ANA1A 0x1A
799#define PHY_ANA1A_TXR_LOOPBACK 0x2000
800#define PHY_ANA1A_RXT_BIST 0x0500
801#define PHY_ANA1A_TXR_BIST 0x0040
802#define PHY_ANA1A_REV 0x0006
757#define PHY_FLD1 0x1B 803#define PHY_FLD1 0x1B
758#define PHY_FLD2 0x1C 804#define PHY_FLD2 0x1C
759#define PHY_FLD3 0x1D 805#define PHY_FLD3 0x1D
806#define PHY_FLD3_TIMER_4 0x0800
807#define PHY_FLD3_TIMER_6 0x0020
808#define PHY_FLD3_RXDELINK 0x0004
809#define PHY_ANA1D 0x1D
810#define PHY_ANA1D_DEBUG_ADDR 0x0004
811#define _PHY_FLD0 0x1D
812#define _PHY_FLD0_CLK_REQ_20C 0x8000
813#define _PHY_FLD0_RX_IDLE_EN 0x1000
814#define _PHY_FLD0_BIT_ERR_RSTN 0x0800
815#define _PHY_FLD0_BER_COUNT 0x01E0
816#define _PHY_FLD0_BER_TIMER 0x001E
817#define _PHY_FLD0_CHECK_EN 0x0001
818
760#define PHY_FLD4 0x1E 819#define PHY_FLD4 0x1E
820#define PHY_FLD4_FLDEN_SEL 0x4000
821#define PHY_FLD4_REQ_REF 0x2000
822#define PHY_FLD4_RXAMP_OFF 0x1000
823#define PHY_FLD4_REQ_ADDA 0x0800
824#define PHY_FLD4_BER_COUNT 0x00E0
825#define PHY_FLD4_BER_TIMER 0x000A
826#define PHY_FLD4_BER_CHK_EN 0x0001
827#define PHY_DIG1E 0x1E
828#define PHY_DIG1E_REV 0x4000
829#define PHY_DIG1E_D0_X_D1 0x1000
830#define PHY_DIG1E_RX_ON_HOST 0x0800
831#define PHY_DIG1E_RCLK_REF_HOST 0x0400
832#define PHY_DIG1E_RCLK_TX_EN_KEEP 0x0040
833#define PHY_DIG1E_RCLK_TX_TERM_KEEP 0x0020
834#define PHY_DIG1E_RCLK_RX_EIDLE_ON 0x0010
835#define PHY_DIG1E_TX_TERM_KEEP 0x0008
836#define PHY_DIG1E_RX_TERM_KEEP 0x0004
837#define PHY_DIG1E_TX_EN_KEEP 0x0002
838#define PHY_DIG1E_RX_EN_KEEP 0x0001
761#define PHY_DUM_REG 0x1F 839#define PHY_DUM_REG 0x1F
762 840
763#define LCTLR 0x80
764#define LCTLR_EXT_SYNC 0x80
765#define LCTLR_COMMON_CLOCK_CFG 0x40
766#define LCTLR_RETRAIN_LINK 0x20
767#define LCTLR_LINK_DISABLE 0x10
768#define LCTLR_RCB 0x08
769#define LCTLR_RESERVED 0x04
770#define LCTLR_ASPM_CTL_MASK 0x03
771
772#define PCR_SETTING_REG1 0x724 841#define PCR_SETTING_REG1 0x724
773#define PCR_SETTING_REG2 0x814 842#define PCR_SETTING_REG2 0x814
774#define PCR_SETTING_REG3 0x747 843#define PCR_SETTING_REG3 0x747
775 844
776/* Phy bits */
777#define PHY_PCR_FORCE_CODE 0xB000
778#define PHY_PCR_OOBS_CALI_50 0x0800
779#define PHY_PCR_OOBS_VCM_08 0x0200
780#define PHY_PCR_OOBS_SEN_90 0x0040
781#define PHY_PCR_RSSI_EN 0x0002
782
783#define PHY_RCR1_ADP_TIME 0x0100
784#define PHY_RCR1_VCO_COARSE 0x001F
785
786#define PHY_RCR2_EMPHASE_EN 0x8000
787#define PHY_RCR2_NADJR 0x4000
788#define PHY_RCR2_CDR_CP_10 0x0400
789#define PHY_RCR2_CDR_SR_2 0x0100
790#define PHY_RCR2_FREQSEL_12 0x0040
791#define PHY_RCR2_CPADJEN 0x0020
792#define PHY_RCR2_CDR_SC_8 0x0008
793#define PHY_RCR2_CALIB_LATE 0x0002
794
795#define PHY_RDR_RXDSEL_1_9 0x4000
796
797#define PHY_TUNE_TUNEREF_1_0 0x4000
798#define PHY_TUNE_VBGSEL_1252 0x0C00
799#define PHY_TUNE_SDBUS_33 0x0200
800#define PHY_TUNE_TUNED18 0x01C0
801#define PHY_TUNE_TUNED12 0X0020
802
803#define PHY_BPCR_IBRXSEL 0x0400
804#define PHY_BPCR_IBTXSEL 0x0100
805#define PHY_BPCR_IB_FILTER 0x0080
806#define PHY_BPCR_CMIRROR_EN 0x0040
807
808#define PHY_REG_REV_RESV 0xE000
809#define PHY_REG_REV_RXIDLE_LATCHED 0x1000
810#define PHY_REG_REV_P1_EN 0x0800
811#define PHY_REG_REV_RXIDLE_EN 0x0400
812#define PHY_REG_REV_CLKREQ_DLY_TIMER_1_0 0x0040
813#define PHY_REG_REV_STOP_CLKRD 0x0020
814#define PHY_REG_REV_RX_PWST 0x0008
815#define PHY_REG_REV_STOP_CLKWR 0x0004
816
817#define PHY_FLD3_TIMER_4 0x7800
818#define PHY_FLD3_TIMER_6 0x00E0
819#define PHY_FLD3_RXDELINK 0x0004
820
821#define PHY_FLD4_FLDEN_SEL 0x4000
822#define PHY_FLD4_REQ_REF 0x2000
823#define PHY_FLD4_RXAMP_OFF 0x1000
824#define PHY_FLD4_REQ_ADDA 0x0800
825#define PHY_FLD4_BER_COUNT 0x00E0
826#define PHY_FLD4_BER_TIMER 0x000A
827#define PHY_FLD4_BER_CHK_EN 0x0001
828
829#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0) 845#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
830 846
831struct rtsx_pcr; 847struct rtsx_pcr;
@@ -835,6 +851,8 @@ struct pcr_handle {
835}; 851};
836 852
837struct pcr_ops { 853struct pcr_ops {
854 int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
855 int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
838 int (*extra_init_hw)(struct rtsx_pcr *pcr); 856 int (*extra_init_hw)(struct rtsx_pcr *pcr);
839 int (*optimize_phy)(struct rtsx_pcr *pcr); 857 int (*optimize_phy)(struct rtsx_pcr *pcr);
840 int (*turn_on_led)(struct rtsx_pcr *pcr); 858 int (*turn_on_led)(struct rtsx_pcr *pcr);
@@ -856,6 +874,7 @@ enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
856struct rtsx_pcr { 874struct rtsx_pcr {
857 struct pci_dev *pci; 875 struct pci_dev *pci;
858 unsigned int id; 876 unsigned int id;
877 int pcie_cap;
859 878
860 /* pci resources */ 879 /* pci resources */
861 unsigned long addr; 880 unsigned long addr;
@@ -928,6 +947,8 @@ struct rtsx_pcr {
928 const struct pcr_ops *ops; 947 const struct pcr_ops *ops;
929 enum PDEV_STAT state; 948 enum PDEV_STAT state;
930 949
950 u16 reg_pm_ctrl3;
951
931 int num_slots; 952 int num_slots;
932 struct rtsx_slot *slots; 953 struct rtsx_slot *slots;
933}; 954};
@@ -935,6 +956,10 @@ struct rtsx_pcr {
935#define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid)) 956#define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
936#define PCI_VID(pcr) ((pcr)->pci->vendor) 957#define PCI_VID(pcr) ((pcr)->pci->vendor)
937#define PCI_PID(pcr) ((pcr)->pci->device) 958#define PCI_PID(pcr) ((pcr)->pci->device)
959#define is_version(pcr, pid, ver) \
960 (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
961#define pcr_dbg(pcr, fmt, arg...) \
962 dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
938 963
939#define SDR104_PHASE(val) ((val) & 0xFF) 964#define SDR104_PHASE(val) ((val) & 0xFF)
940#define SDR50_PHASE(val) (((val) >> 8) & 0xFF) 965#define SDR50_PHASE(val) (((val) >> 8) & 0xFF)
@@ -1004,4 +1029,17 @@ static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
1004 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val); 1029 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
1005} 1030}
1006 1031
1032static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
1033 u16 mask, u16 append)
1034{
1035 int err;
1036 u16 val;
1037
1038 err = rtsx_pci_read_phy_register(pcr, addr, &val);
1039 if (err < 0)
1040 return err;
1041
1042 return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
1043}
1044
1007#endif 1045#endif
diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h
index 3fdb7cfbffb3..75115384f3fc 100644
--- a/include/linux/mfd/samsung/core.h
+++ b/include/linux/mfd/samsung/core.h
@@ -58,13 +58,7 @@ enum sec_device_type {
58 * @irq_base: Base IRQ number for device, required for IRQs 58 * @irq_base: Base IRQ number for device, required for IRQs
59 * @irq: Generic IRQ number for device 59 * @irq: Generic IRQ number for device
60 * @irq_data: Runtime data structure for IRQ controller 60 * @irq_data: Runtime data structure for IRQ controller
61 * @ono: Power onoff IRQ number for s5m87xx
62 * @wakeup: Whether or not this is a wakeup device 61 * @wakeup: Whether or not this is a wakeup device
63 * @wtsr_smpl: Whether or not to enable in RTC driver the Watchdog
64 * Timer Software Reset (registers set to default value
65 * after PWRHOLD falling) and Sudden Momentary Power Loss
66 * (PMIC will enter power on sequence after short drop in
67 * VBATT voltage).
68 */ 62 */
69struct sec_pmic_dev { 63struct sec_pmic_dev {
70 struct device *dev; 64 struct device *dev;
@@ -77,9 +71,7 @@ struct sec_pmic_dev {
77 int irq; 71 int irq;
78 struct regmap_irq_chip_data *irq_data; 72 struct regmap_irq_chip_data *irq_data;
79 73
80 int ono;
81 bool wakeup; 74 bool wakeup;
82 bool wtsr_smpl;
83}; 75};
84 76
85int sec_irq_init(struct sec_pmic_dev *sec_pmic); 77int sec_irq_init(struct sec_pmic_dev *sec_pmic);
@@ -95,7 +87,6 @@ struct sec_platform_data {
95 int irq_base; 87 int irq_base;
96 int (*cfg_pmic_irq)(void); 88 int (*cfg_pmic_irq)(void);
97 89
98 int ono;
99 bool wakeup; 90 bool wakeup;
100 bool buck_voltage_lock; 91 bool buck_voltage_lock;
101 92
diff --git a/include/linux/mfd/samsung/irq.h b/include/linux/mfd/samsung/irq.h
index f35af7361b60..667aa40486dd 100644
--- a/include/linux/mfd/samsung/irq.h
+++ b/include/linux/mfd/samsung/irq.h
@@ -74,8 +74,8 @@ enum s2mps11_irq {
74 S2MPS11_IRQ_MRB, 74 S2MPS11_IRQ_MRB,
75 75
76 S2MPS11_IRQ_RTC60S, 76 S2MPS11_IRQ_RTC60S,
77 S2MPS11_IRQ_RTCA0,
78 S2MPS11_IRQ_RTCA1, 77 S2MPS11_IRQ_RTCA1,
78 S2MPS11_IRQ_RTCA0,
79 S2MPS11_IRQ_SMPL, 79 S2MPS11_IRQ_SMPL,
80 S2MPS11_IRQ_RTC1S, 80 S2MPS11_IRQ_RTC1S,
81 S2MPS11_IRQ_WTSR, 81 S2MPS11_IRQ_WTSR,
diff --git a/include/linux/mfd/sky81452.h b/include/linux/mfd/sky81452.h
new file mode 100644
index 000000000000..b0925fa3e9ef
--- /dev/null
+++ b/include/linux/mfd/sky81452.h
@@ -0,0 +1,31 @@
1/*
2 * sky81452.h SKY81452 MFD driver
3 *
4 * Copyright 2014 Skyworks Solutions Inc.
5 * Author : Gyungoh Yoo <jack.yoo@skyworksinc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef _SKY81452_H
21#define _SKY81452_H
22
23#include <linux/platform_data/sky81452-backlight.h>
24#include <linux/regulator/machine.h>
25
26struct sky81452_platform_data {
27 struct sky81452_bl_platform_data *bl_pdata;
28 struct regulator_init_data *regulator_init_data;
29};
30
31#endif
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
index 3f4e994ace2b..1fd50dcfe47c 100644
--- a/include/linux/mfd/ti_am335x_tscadc.h
+++ b/include/linux/mfd/ti_am335x_tscadc.h
@@ -128,6 +128,7 @@
128 128
129/* Sequencer Status */ 129/* Sequencer Status */
130#define SEQ_STATUS BIT(5) 130#define SEQ_STATUS BIT(5)
131#define CHARGE_STEP 0x11
131 132
132#define ADC_CLK 3000000 133#define ADC_CLK 3000000
133#define TOTAL_STEPS 16 134#define TOTAL_STEPS 16
diff --git a/include/linux/platform_data/sky81452-backlight.h b/include/linux/platform_data/sky81452-backlight.h
new file mode 100644
index 000000000000..1231e9bb00f1
--- /dev/null
+++ b/include/linux/platform_data/sky81452-backlight.h
@@ -0,0 +1,46 @@
1/*
2 * sky81452.h SKY81452 backlight driver
3 *
4 * Copyright 2014 Skyworks Solutions Inc.
5 * Author : Gyungoh Yoo <jack.yoo@skyworksinc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef _SKY81452_BACKLIGHT_H
21#define _SKY81452_BACKLIGHT_H
22
23/**
24 * struct sky81452_platform_data
25 * @name: backlight driver name.
26 If it is not defined, default name is lcd-backlight.
27 * @gpio_enable:GPIO number which control EN pin
28 * @enable: Enable mask for current sink channel 1, 2, 3, 4, 5 and 6.
29 * @ignore_pwm: true if DPWMI should be ignored.
30 * @dpwm_mode: true is DPWM dimming mode, otherwise Analog dimming mode.
31 * @phase_shift:true is phase shift mode.
32 * @short_detecion_threshold: It should be one of 4, 5, 6 and 7V.
33 * @boost_current_limit: It should be one of 2300, 2750mA.
34 */
35struct sky81452_bl_platform_data {
36 const char *name;
37 int gpio_enable;
38 unsigned int enable;
39 bool ignore_pwm;
40 bool dpwm_mode;
41 bool phase_shift;
42 unsigned int short_detection_threshold;
43 unsigned int boost_current_limit;
44};
45
46#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-12 16:40:40 -0400