Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "New core SoC-specific changes.

  New platforms:
   * Introduction of a vendor, Hisilicon, and one of their SoCs with
     some random numerical product name.
   * Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m,
     i.e. !MMU).
   * Marvell Berlin series of SoCs, which include the one in Chromecast.
   * MOXA platform support, ARM9-based platform used mostly in
     industrial products
   * Support for Freescale's i.MX50 SoC.

  Other work:
   * Renesas work for new platforms and drivers, and conversion over to
     more multiplatform-friendly device registration schemes.
   * SMP support for Allwinner sunxi platforms.
   * ... plus a bunch of other stuff across various platforms"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (201 commits)
  ARM: tegra: fix tegra_powergate_sequence_power_up() inline
  ARM: msm_defconfig: Update for multi-platform
  ARM: msm: Move MSM's DT based hardware to multi-platform support
  ARM: msm: Only build timer.c if required
  ARM: msm: Only build clock.c on proc_comm based platforms
  ARM: ux500: Enable system suspend with WFI support
  ARM: ux500: turn on PRINTK_TIME in u8500_defconfig
  ARM: shmobile: r8a7790: Fix I2C controller names
  ARM: msm: Simplify ARCH_MSM_DT config
  ARM: msm: Add support for MSM8974 SoC
  ARM: sunxi: select ARM_PSCI
  MAINTAINERS: Update Allwinner sunXi maintainer files
  ARM: sunxi: Select RESET_CONTROLLER
  ARM: imx: improve the comment of CCM lpm SW workaround
  ARM: imx: improve status check of clock gate
  ARM: imx: add necessary interface for pfd
  ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100
  ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support
  ARM: imx: Add cpu frequency scaling support
  ARM i.MX35: Add devicetree support.
  ...

6 files changed, 465 insertions, 3 deletions

diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
new file mode 100644
index 000000000000..5f2667ecd98e
--- /dev/null
+++ b/include/dt-bindings/clock/imx5-clock.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX5_H
+#define __DT_BINDINGS_CLOCK_IMX5_H
+
+#define IMX5_CLK_DUMMY                  0
+#define IMX5_CLK_CKIL                   1
+#define IMX5_CLK_OSC                    2
+#define IMX5_CLK_CKIH1                  3
+#define IMX5_CLK_CKIH2                  4
+#define IMX5_CLK_AHB                    5
+#define IMX5_CLK_IPG                    6
+#define IMX5_CLK_AXI_A                  7
+#define IMX5_CLK_AXI_B                  8
+#define IMX5_CLK_UART_PRED              9
+#define IMX5_CLK_UART_ROOT              10
+#define IMX5_CLK_ESDHC_A_PRED           11
+#define IMX5_CLK_ESDHC_B_PRED           12
+#define IMX5_CLK_ESDHC_C_SEL            13
+#define IMX5_CLK_ESDHC_D_SEL            14
+#define IMX5_CLK_EMI_SEL                15
+#define IMX5_CLK_EMI_SLOW_PODF          16
+#define IMX5_CLK_NFC_PODF               17
+#define IMX5_CLK_ECSPI_PRED             18
+#define IMX5_CLK_ECSPI_PODF             19
+#define IMX5_CLK_USBOH3_PRED            20
+#define IMX5_CLK_USBOH3_PODF            21
+#define IMX5_CLK_USB_PHY_PRED           22
+#define IMX5_CLK_USB_PHY_PODF           23
+#define IMX5_CLK_CPU_PODF               24
+#define IMX5_CLK_DI_PRED                25
+#define IMX5_CLK_TVE_SEL                27
+#define IMX5_CLK_UART1_IPG_GATE         28
+#define IMX5_CLK_UART1_PER_GATE         29
+#define IMX5_CLK_UART2_IPG_GATE         30
+#define IMX5_CLK_UART2_PER_GATE         31
+#define IMX5_CLK_UART3_IPG_GATE         32
+#define IMX5_CLK_UART3_PER_GATE         33
+#define IMX5_CLK_I2C1_GATE              34
+#define IMX5_CLK_I2C2_GATE              35
+#define IMX5_CLK_GPT_IPG_GATE           36
+#define IMX5_CLK_PWM1_IPG_GATE          37
+#define IMX5_CLK_PWM1_HF_GATE           38
+#define IMX5_CLK_PWM2_IPG_GATE          39
+#define IMX5_CLK_PWM2_HF_GATE           40
+#define IMX5_CLK_GPT_HF_GATE            41
+#define IMX5_CLK_FEC_GATE               42
+#define IMX5_CLK_USBOH3_PER_GATE        43
+#define IMX5_CLK_ESDHC1_IPG_GATE        44
+#define IMX5_CLK_ESDHC2_IPG_GATE        45
+#define IMX5_CLK_ESDHC3_IPG_GATE        46
+#define IMX5_CLK_ESDHC4_IPG_GATE        47
+#define IMX5_CLK_SSI1_IPG_GATE          48
+#define IMX5_CLK_SSI2_IPG_GATE          49
+#define IMX5_CLK_SSI3_IPG_GATE          50
+#define IMX5_CLK_ECSPI1_IPG_GATE        51
+#define IMX5_CLK_ECSPI1_PER_GATE        52
+#define IMX5_CLK_ECSPI2_IPG_GATE        53
+#define IMX5_CLK_ECSPI2_PER_GATE        54
+#define IMX5_CLK_CSPI_IPG_GATE          55
+#define IMX5_CLK_SDMA_GATE              56
+#define IMX5_CLK_EMI_SLOW_GATE          57
+#define IMX5_CLK_IPU_SEL                58
+#define IMX5_CLK_IPU_GATE               59
+#define IMX5_CLK_NFC_GATE               60
+#define IMX5_CLK_IPU_DI1_GATE           61
+#define IMX5_CLK_VPU_SEL                62
+#define IMX5_CLK_VPU_GATE               63
+#define IMX5_CLK_VPU_REFERENCE_GATE     64
+#define IMX5_CLK_UART4_IPG_GATE         65
+#define IMX5_CLK_UART4_PER_GATE         66
+#define IMX5_CLK_UART5_IPG_GATE         67
+#define IMX5_CLK_UART5_PER_GATE         68
+#define IMX5_CLK_TVE_GATE               69
+#define IMX5_CLK_TVE_PRED               70
+#define IMX5_CLK_ESDHC1_PER_GATE        71
+#define IMX5_CLK_ESDHC2_PER_GATE        72
+#define IMX5_CLK_ESDHC3_PER_GATE        73
+#define IMX5_CLK_ESDHC4_PER_GATE        74
+#define IMX5_CLK_USB_PHY_GATE           75
+#define IMX5_CLK_HSI2C_GATE             76
+#define IMX5_CLK_MIPI_HSC1_GATE         77
+#define IMX5_CLK_MIPI_HSC2_GATE         78
+#define IMX5_CLK_MIPI_ESC_GATE          79
+#define IMX5_CLK_MIPI_HSP_GATE          80
+#define IMX5_CLK_LDB_DI1_DIV_3_5        81
+#define IMX5_CLK_LDB_DI1_DIV            82
+#define IMX5_CLK_LDB_DI0_DIV_3_5        83
+#define IMX5_CLK_LDB_DI0_DIV            84
+#define IMX5_CLK_LDB_DI1_GATE           85
+#define IMX5_CLK_CAN2_SERIAL_GATE       86
+#define IMX5_CLK_CAN2_IPG_GATE          87
+#define IMX5_CLK_I2C3_GATE              88
+#define IMX5_CLK_LP_APM                 89
+#define IMX5_CLK_PERIPH_APM             90
+#define IMX5_CLK_MAIN_BUS               91
+#define IMX5_CLK_AHB_MAX                92
+#define IMX5_CLK_AIPS_TZ1               93
+#define IMX5_CLK_AIPS_TZ2               94
+#define IMX5_CLK_TMAX1                  95
+#define IMX5_CLK_TMAX2                  96
+#define IMX5_CLK_TMAX3                  97
+#define IMX5_CLK_SPBA                   98
+#define IMX5_CLK_UART_SEL               99
+#define IMX5_CLK_ESDHC_A_SEL            100
+#define IMX5_CLK_ESDHC_B_SEL            101
+#define IMX5_CLK_ESDHC_A_PODF           102
+#define IMX5_CLK_ESDHC_B_PODF           103
+#define IMX5_CLK_ECSPI_SEL              104
+#define IMX5_CLK_USBOH3_SEL             105
+#define IMX5_CLK_USB_PHY_SEL            106
+#define IMX5_CLK_IIM_GATE               107
+#define IMX5_CLK_USBOH3_GATE            108
+#define IMX5_CLK_EMI_FAST_GATE          109
+#define IMX5_CLK_IPU_DI0_GATE           110
+#define IMX5_CLK_GPC_DVFS               111
+#define IMX5_CLK_PLL1_SW                112
+#define IMX5_CLK_PLL2_SW                113
+#define IMX5_CLK_PLL3_SW                114
+#define IMX5_CLK_IPU_DI0_SEL            115
+#define IMX5_CLK_IPU_DI1_SEL            116
+#define IMX5_CLK_TVE_EXT_SEL            117
+#define IMX5_CLK_MX51_MIPI              118
+#define IMX5_CLK_PLL4_SW                119
+#define IMX5_CLK_LDB_DI1_SEL            120
+#define IMX5_CLK_DI_PLL4_PODF           121
+#define IMX5_CLK_LDB_DI0_SEL            122
+#define IMX5_CLK_LDB_DI0_GATE           123
+#define IMX5_CLK_USB_PHY1_GATE          124
+#define IMX5_CLK_USB_PHY2_GATE          125
+#define IMX5_CLK_PER_LP_APM             126
+#define IMX5_CLK_PER_PRED1              127
+#define IMX5_CLK_PER_PRED2              128
+#define IMX5_CLK_PER_PODF               129
+#define IMX5_CLK_PER_ROOT               130
+#define IMX5_CLK_SSI_APM                131
+#define IMX5_CLK_SSI1_ROOT_SEL          132
+#define IMX5_CLK_SSI2_ROOT_SEL          133
+#define IMX5_CLK_SSI3_ROOT_SEL          134
+#define IMX5_CLK_SSI_EXT1_SEL           135
+#define IMX5_CLK_SSI_EXT2_SEL           136
+#define IMX5_CLK_SSI_EXT1_COM_SEL       137
+#define IMX5_CLK_SSI_EXT2_COM_SEL       138
+#define IMX5_CLK_SSI1_ROOT_PRED         139
+#define IMX5_CLK_SSI1_ROOT_PODF         140
+#define IMX5_CLK_SSI2_ROOT_PRED         141
+#define IMX5_CLK_SSI2_ROOT_PODF         142
+#define IMX5_CLK_SSI_EXT1_PRED          143
+#define IMX5_CLK_SSI_EXT1_PODF          144
+#define IMX5_CLK_SSI_EXT2_PRED          145
+#define IMX5_CLK_SSI_EXT2_PODF          146
+#define IMX5_CLK_SSI1_ROOT_GATE         147
+#define IMX5_CLK_SSI2_ROOT_GATE         148
+#define IMX5_CLK_SSI3_ROOT_GATE         149
+#define IMX5_CLK_SSI_EXT1_GATE          150
+#define IMX5_CLK_SSI_EXT2_GATE          151
+#define IMX5_CLK_EPIT1_IPG_GATE         152
+#define IMX5_CLK_EPIT1_HF_GATE          153
+#define IMX5_CLK_EPIT2_IPG_GATE         154
+#define IMX5_CLK_EPIT2_HF_GATE          155
+#define IMX5_CLK_CAN_SEL                156
+#define IMX5_CLK_CAN1_SERIAL_GATE       157
+#define IMX5_CLK_CAN1_IPG_GATE          158
+#define IMX5_CLK_OWIRE_GATE             159
+#define IMX5_CLK_GPU3D_SEL              160
+#define IMX5_CLK_GPU2D_SEL              161
+#define IMX5_CLK_GPU3D_GATE             162
+#define IMX5_CLK_GPU2D_GATE             163
+#define IMX5_CLK_GARB_GATE              164
+#define IMX5_CLK_CKO1_SEL               165
+#define IMX5_CLK_CKO1_PODF              166
+#define IMX5_CLK_CKO1                   167
+#define IMX5_CLK_CKO2_SEL               168
+#define IMX5_CLK_CKO2_PODF              169
+#define IMX5_CLK_CKO2                   170
+#define IMX5_CLK_SRTC_GATE              171
+#define IMX5_CLK_PATA_GATE              172
+#define IMX5_CLK_SATA_GATE              173
+#define IMX5_CLK_SPDIF_XTAL_SEL         174
+#define IMX5_CLK_SPDIF0_SEL             175
+#define IMX5_CLK_SPDIF1_SEL             176
+#define IMX5_CLK_SPDIF0_PRED            177
+#define IMX5_CLK_SPDIF0_PODF            178
+#define IMX5_CLK_SPDIF1_PRED            179
+#define IMX5_CLK_SPDIF1_PODF            180
+#define IMX5_CLK_SPDIF0_COM_SEL         181
+#define IMX5_CLK_SPDIF1_COM_SEL         182
+#define IMX5_CLK_SPDIF0_GATE            183
+#define IMX5_CLK_SPDIF1_GATE            184
+#define IMX5_CLK_SPDIF_IPG_GATE         185
+#define IMX5_CLK_OCRAM                  186
+#define IMX5_CLK_SAHARA_IPG_GATE        187
+#define IMX5_CLK_SATA_REF               188
+#define IMX5_CLK_END                    189
+
+#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
index 7fcdf90879f2..7cf5c9969336 100644
--- a/include/dt-bindings/clock/imx6sl-clock.h
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -143,6 +143,8 @@
 #define IMX6SL_CLK_USDHC2               130
 #define IMX6SL_CLK_USDHC3               131
 #define IMX6SL_CLK_USDHC4               132
-#define IMX6SL_CLK_CLK_END              133
+#define IMX6SL_CLK_PLL4_AUDIO_DIV       133
+#define IMX6SL_CLK_SPBA                 134
+#define IMX6SL_CLK_END                  135
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
new file mode 100644
index 000000000000..420f0b00ae1e
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_H__
+
+/* CPG */
+#define R8A7790_CLK_MAIN                0
+#define R8A7790_CLK_PLL0                1
+#define R8A7790_CLK_PLL1                2
+#define R8A7790_CLK_PLL3                3
+#define R8A7790_CLK_LB                  4
+#define R8A7790_CLK_QSPI                5
+#define R8A7790_CLK_SDH                 6
+#define R8A7790_CLK_SD0                 7
+#define R8A7790_CLK_SD1                 8
+#define R8A7790_CLK_Z                   9
+
+/* MSTP1 */
+#define R8A7790_CLK_TMU1                11
+#define R8A7790_CLK_TMU3                21
+#define R8A7790_CLK_TMU2                22
+#define R8A7790_CLK_CMT0                24
+#define R8A7790_CLK_TMU0                25
+#define R8A7790_CLK_VSP1_DU1            27
+#define R8A7790_CLK_VSP1_DU0            28
+#define R8A7790_CLK_VSP1_RT             30
+#define R8A7790_CLK_VSP1_SY             31
+
+/* MSTP2 */
+#define R8A7790_CLK_SCIFA2              2
+#define R8A7790_CLK_SCIFA1              3
+#define R8A7790_CLK_SCIFA0              4
+#define R8A7790_CLK_SCIFB0              6
+#define R8A7790_CLK_SCIFB1              7
+#define R8A7790_CLK_SCIFB2              16
+#define R8A7790_CLK_SYS_DMAC0           18
+#define R8A7790_CLK_SYS_DMAC1           19
+
+/* MSTP3 */
+#define R8A7790_CLK_TPU0                4
+#define R8A7790_CLK_MMCIF1              5
+#define R8A7790_CLK_SDHI3               11
+#define R8A7790_CLK_SDHI2               12
+#define R8A7790_CLK_SDHI1               13
+#define R8A7790_CLK_SDHI0               14
+#define R8A7790_CLK_MMCIF0              15
+#define R8A7790_CLK_SSUSB               28
+#define R8A7790_CLK_CMT1                29
+#define R8A7790_CLK_USBDMAC0            30
+#define R8A7790_CLK_USBDMAC1            31
+
+/* MSTP5 */
+#define R8A7790_CLK_THERMAL             22
+#define R8A7790_CLK_PWM                 23
+
+/* MSTP7 */
+#define R8A7790_CLK_EHCI                3
+#define R8A7790_CLK_HSUSB               4
+#define R8A7790_CLK_HSCIF1              16
+#define R8A7790_CLK_HSCIF0              17
+#define R8A7790_CLK_SCIF1               20
+#define R8A7790_CLK_SCIF0               21
+#define R8A7790_CLK_DU2                 22
+#define R8A7790_CLK_DU1                 23
+#define R8A7790_CLK_DU0                 24
+#define R8A7790_CLK_LVDS1               25
+#define R8A7790_CLK_LVDS0               26
+
+/* MSTP8 */
+#define R8A7790_CLK_VIN3                8
+#define R8A7790_CLK_VIN2                9
+#define R8A7790_CLK_VIN1                10
+#define R8A7790_CLK_VIN0                11
+#define R8A7790_CLK_ETHER               13
+#define R8A7790_CLK_SATA1               14
+#define R8A7790_CLK_SATA0               15
+
+/* MSTP9 */
+#define R8A7790_CLK_GPIO5               7
+#define R8A7790_CLK_GPIO4               8
+#define R8A7790_CLK_GPIO3               9
+#define R8A7790_CLK_GPIO2               10
+#define R8A7790_CLK_GPIO1               11
+#define R8A7790_CLK_GPIO0               12
+#define R8A7790_CLK_RCAN1               15
+#define R8A7790_CLK_RCAN0               16
+#define R8A7790_CLK_IICDVFS             26
+#define R8A7790_CLK_I2C3                28
+#define R8A7790_CLK_I2C2                29
+#define R8A7790_CLK_I2C1                30
+#define R8A7790_CLK_I2C0                31
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
new file mode 100644
index 000000000000..df1715b77f96
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
+#define __DT_BINDINGS_CLOCK_R8A7791_H__
+
+/* CPG */
+#define R8A7791_CLK_MAIN                0
+#define R8A7791_CLK_PLL0                1
+#define R8A7791_CLK_PLL1                2
+#define R8A7791_CLK_PLL3                3
+#define R8A7791_CLK_LB                  4
+#define R8A7791_CLK_QSPI                5
+#define R8A7791_CLK_SDH                 6
+#define R8A7791_CLK_SD0                 7
+#define R8A7791_CLK_Z                   8
+
+/* MSTP1 */
+#define R8A7791_CLK_TMU1                11
+#define R8A7791_CLK_TMU3                21
+#define R8A7791_CLK_TMU2                22
+#define R8A7791_CLK_CMT0                24
+#define R8A7791_CLK_TMU0                25
+#define R8A7791_CLK_VSP1_DU1            27
+#define R8A7791_CLK_VSP1_DU0            28
+#define R8A7791_CLK_VSP1_SY             31
+
+/* MSTP2 */
+#define R8A7791_CLK_SCIFA2              2
+#define R8A7791_CLK_SCIFA1              3
+#define R8A7791_CLK_SCIFA0              4
+#define R8A7791_CLK_SCIFB0              6
+#define R8A7791_CLK_SCIFB1              7
+#define R8A7791_CLK_SCIFB2              16
+#define R8A7791_CLK_DMAC                18
+
+/* MSTP3 */
+#define R8A7791_CLK_TPU0                4
+#define R8A7791_CLK_SDHI2               11
+#define R8A7791_CLK_SDHI1               12
+#define R8A7791_CLK_SDHI0               14
+#define R8A7791_CLK_MMCIF0              15
+#define R8A7791_CLK_SSUSB               28
+#define R8A7791_CLK_CMT1                29
+#define R8A7791_CLK_USBDMAC0            30
+#define R8A7791_CLK_USBDMAC1            31
+
+/* MSTP5 */
+#define R8A7791_CLK_THERMAL             22
+#define R8A7791_CLK_PWM                 23
+
+/* MSTP7 */
+#define R8A7791_CLK_HSUSB               4
+#define R8A7791_CLK_HSCIF2              13
+#define R8A7791_CLK_SCIF5               14
+#define R8A7791_CLK_SCIF4               15
+#define R8A7791_CLK_HSCIF1              16
+#define R8A7791_CLK_HSCIF0              17
+#define R8A7791_CLK_SCIF3               18
+#define R8A7791_CLK_SCIF2               19
+#define R8A7791_CLK_SCIF1               20
+#define R8A7791_CLK_SCIF0               21
+#define R8A7791_CLK_DU1                 23
+#define R8A7791_CLK_DU0                 24
+#define R8A7791_CLK_LVDS0               26
+
+/* MSTP8 */
+#define R8A7791_CLK_VIN2                9
+#define R8A7791_CLK_VIN1                10
+#define R8A7791_CLK_VIN0                11
+#define R8A7791_CLK_ETHER               13
+#define R8A7791_CLK_SATA1               14
+#define R8A7791_CLK_SATA0               15
+
+/* MSTP9 */
+#define R8A7791_CLK_GPIO7               4
+#define R8A7791_CLK_GPIO6               5
+#define R8A7791_CLK_GPIO5               7
+#define R8A7791_CLK_GPIO4               8
+#define R8A7791_CLK_GPIO3               9
+#define R8A7791_CLK_GPIO2               10
+#define R8A7791_CLK_GPIO1               11
+#define R8A7791_CLK_GPIO0               12
+#define R8A7791_CLK_RCAN1               15
+#define R8A7791_CLK_RCAN0               16
+#define R8A7791_CLK_I2C5                25
+#define R8A7791_CLK_IICDVFS             26
+#define R8A7791_CLK_I2C4                27
+#define R8A7791_CLK_I2C3                28
+#define R8A7791_CLK_I2C2                29
+#define R8A7791_CLK_I2C1                30
+#define R8A7791_CLK_I2C0                31
+
+/* MSTP11 */
+#define R8A7791_CLK_SCIFA3              6
+#define R8A7791_CLK_SCIFA4              7
+#define R8A7791_CLK_SCIFA5              8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 4aa2b48cd151..a91602951d3d 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -160,6 +160,10 @@
 #define VF610_CLK_GPU2D                 147
 #define VF610_CLK_ENET0                 148
 #define VF610_CLK_ENET1                 149
-#define VF610_CLK_END                   150
+#define VF610_CLK_DMAMUX0               150
+#define VF610_CLK_DMAMUX1               151
+#define VF610_CLK_DMAMUX2               152
+#define VF610_CLK_DMAMUX3               153
+#define VF610_CLK_END                   154
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h
index afe442d2629a..46f0a07812b4 100644
--- a/include/linux/tegra-powergate.h
+++ b/include/linux/tegra-powergate.h
@@ -38,14 +38,49 @@ struct reset_control;
 #define TEGRA_POWERGATE_CPU0    14
 #define TEGRA_POWERGATE_C0NC    15
 #define TEGRA_POWERGATE_C1NC    16
+#define TEGRA_POWERGATE_SOR     17
 #define TEGRA_POWERGATE_DIS     18
 #define TEGRA_POWERGATE_DISB    19
 #define TEGRA_POWERGATE_XUSBA   20
 #define TEGRA_POWERGATE_XUSBB   21
 #define TEGRA_POWERGATE_XUSBC   22
+#define TEGRA_POWERGATE_VIC     23
+#define TEGRA_POWERGATE_IRAM    24
 
 #define TEGRA_POWERGATE_3D0     TEGRA_POWERGATE_3D
 
+#define TEGRA_IO_RAIL_CSIA      0
+#define TEGRA_IO_RAIL_CSIB      1
+#define TEGRA_IO_RAIL_DSI       2
+#define TEGRA_IO_RAIL_MIPI_BIAS 3
+#define TEGRA_IO_RAIL_PEX_BIAS  4
+#define TEGRA_IO_RAIL_PEX_CLK1  5
+#define TEGRA_IO_RAIL_PEX_CLK2  6
+#define TEGRA_IO_RAIL_USB0      9
+#define TEGRA_IO_RAIL_USB1      10
+#define TEGRA_IO_RAIL_USB2      11
+#define TEGRA_IO_RAIL_USB_BIAS  12
+#define TEGRA_IO_RAIL_NAND      13
+#define TEGRA_IO_RAIL_UART      14
+#define TEGRA_IO_RAIL_BB        15
+#define TEGRA_IO_RAIL_AUDIO     17
+#define TEGRA_IO_RAIL_HSIC      19
+#define TEGRA_IO_RAIL_COMP      22
+#define TEGRA_IO_RAIL_HDMI      28
+#define TEGRA_IO_RAIL_PEX_CNTRL 32
+#define TEGRA_IO_RAIL_SDMMC1    33
+#define TEGRA_IO_RAIL_SDMMC3    34
+#define TEGRA_IO_RAIL_SDMMC4    35
+#define TEGRA_IO_RAIL_CAM       36
+#define TEGRA_IO_RAIL_RES       37
+#define TEGRA_IO_RAIL_HV        38
+#define TEGRA_IO_RAIL_DSIB      39
+#define TEGRA_IO_RAIL_DSIC      40
+#define TEGRA_IO_RAIL_DSID      41
+#define TEGRA_IO_RAIL_CSIE      44
+#define TEGRA_IO_RAIL_LVDS      57
+#define TEGRA_IO_RAIL_SYS_DDC   58
+
 #ifdef CONFIG_ARCH_TEGRA
 int tegra_powergate_is_powered(int id);
 int tegra_powergate_power_on(int id);
@@ -55,6 +90,9 @@ int tegra_powergate_remove_clamping(int id);
 /* Must be called with clk disabled, and returns with clk enabled */
 int tegra_powergate_sequence_power_up(int id, struct clk *clk,
                                       struct reset_control *rst);
+
+int tegra_io_rail_power_on(int id);
+int tegra_io_rail_power_off(int id);
 #else
 static inline int tegra_powergate_is_powered(int id)
 {
@@ -77,7 +115,17 @@ static inline int tegra_powergate_remove_clamping(int id)
 }
 
 static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk,
-                                                    struct reset_control *rst);
+                                                    struct reset_control *rst)
+{
+        return -ENOSYS;
+}
+
+static inline int tegra_io_rail_power_on(int id)
+{
+        return -ENOSYS;
+}
+
+static inline int tegra_io_rail_power_off(int id)
 {
         return -ENOSYS;
 }