clk: samsung: exynos5433: Add clocks for CMU_APOLLO domain

This patch adds the mux/divider/gate clocks for CMU_APOLLO domain
which generates the clocks for Cortex-A53 Quad-core processsor.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
[s.nawrocki@samsung.com: Renamed pclk_pmu_sysreg_apollo to pclk_sysreg_apollo]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

1 files changed, 37 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index fef8893c3ec2..90184e3a42d5 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -854,4 +854,41 @@
 
 #define GSCL_NR_CLK                                     29
 
+/* CMU_APOLLO */
+#define CLK_FOUT_APOLLO_PLL                             1
+
+#define CLK_MOUT_APOLLO_PLL                             2
+#define CLK_MOUT_BUS_PLL_APOLLO_USER                    3
+#define CLK_MOUT_APOLLO                                 4
+
+#define CLK_DIV_CNTCLK_APOLLO                           5
+#define CLK_DIV_PCLK_DBG_APOLLO                         6
+#define CLK_DIV_ATCLK_APOLLO                            7
+#define CLK_DIV_PCLK_APOLLO                             8
+#define CLK_DIV_ACLK_APOLLO                             9
+#define CLK_DIV_APOLLO2                                 10
+#define CLK_DIV_APOLLO1                                 11
+#define CLK_DIV_SCLK_HPM_APOLLO                         12
+#define CLK_DIV_APOLLO_PLL                              13
+
+#define CLK_ACLK_ATBDS_APOLLO_3                         14
+#define CLK_ACLK_ATBDS_APOLLO_2                         15
+#define CLK_ACLK_ATBDS_APOLLO_1                         16
+#define CLK_ACLK_ATBDS_APOLLO_0                         17
+#define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS                18
+#define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS                19
+#define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS                20
+#define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS                21
+#define CLK_ACLK_ASYNCACES_APOLLO_CCI                   22
+#define CLK_ACLK_AHB2APB_APOLLOP                        23
+#define CLK_ACLK_APOLLONP_200                           24
+#define CLK_PCLK_ASAPBMST_CSSYS_APOLLO                  25
+#define CLK_PCLK_PMU_APOLLO                             26
+#define CLK_PCLK_SYSREG_APOLLO                          27
+#define CLK_CNTCLK_APOLLO                               28
+#define CLK_SCLK_HPM_APOLLO                             29
+#define CLK_SCLK_APOLLO                                 30
+
+#define APOLLO_NR_CLK                                   31
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */