diff options
author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-07-06 13:29:33 -0400 |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-07-06 13:29:33 -0400 |
commit | dadde13ad86bf45bc71f0663a6ce3dfe5dd4ecc5 (patch) | |
tree | 8dd0a19bc2fd65e05fe7678babbd9a95e53d727b /include | |
parent | 23c1fb52961bc24bd3a8078eefc49eed533b2b38 (diff) | |
parent | 4b3e975e4a06f1710693c5aa51b8f98facfa9863 (diff) |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] Fix scheduling latency issue on 24K, 34K and 74K cores
[MIPS] Add macros to encode processor revisions.
[MIPS] RM7000: Enable ICACHE_REFILLS_WORKAROUND_WAR.
[MIPS] SMTC: Fix cut'n'paste bug in Kconfig.debug
[MIPS] Change libgcc-style functions from lib-y to obj-y
[MIPS] Fix timer/performance interrupt detection
[MIPS] AP/SP: Avoid triggering the 34K E125 performance issue
[MIPS] 64-bit TO_PHYS_MASK macro for RM9000 processors
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-mips/addrspace.h | 1 | ||||
-rw-r--r-- | include/asm-mips/cpu.h | 11 | ||||
-rw-r--r-- | include/asm-mips/mipsregs.h | 2 | ||||
-rw-r--r-- | include/asm-mips/war.h | 18 |
4 files changed, 25 insertions, 7 deletions
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index c6275088cf65..964c5eddc21b 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h | |||
@@ -133,6 +133,7 @@ | |||
133 | || defined (CONFIG_CPU_R4X00) \ | 133 | || defined (CONFIG_CPU_R4X00) \ |
134 | || defined (CONFIG_CPU_R5000) \ | 134 | || defined (CONFIG_CPU_R5000) \ |
135 | || defined (CONFIG_CPU_RM7000) \ | 135 | || defined (CONFIG_CPU_RM7000) \ |
136 | || defined (CONFIG_CPU_RM9000) \ | ||
136 | || defined (CONFIG_CPU_NEVADA) \ | 137 | || defined (CONFIG_CPU_NEVADA) \ |
137 | || defined (CONFIG_CPU_TX49XX) \ | 138 | || defined (CONFIG_CPU_TX49XX) \ |
138 | || defined (CONFIG_CPU_MIPS64) | 139 | || defined (CONFIG_CPU_MIPS64) |
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index d38fdbf845b2..2924069075e0 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h | |||
@@ -125,6 +125,17 @@ | |||
125 | #define PRID_REV_VR4130 0x0080 | 125 | #define PRID_REV_VR4130 0x0080 |
126 | 126 | ||
127 | /* | 127 | /* |
128 | * Older processors used to encode processor version and revision in two | ||
129 | * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores | ||
130 | * have switched to use the 8-bits as 3:3:2 bitfield with the last field as | ||
131 | * the patch number. *ARGH* | ||
132 | */ | ||
133 | #define PRID_REV_ENCODE_44(ver, rev) \ | ||
134 | ((ver) << 4 | (rev)) | ||
135 | #define PRID_REV_ENCODE_332(ver, rev, patch) \ | ||
136 | ((ver) << 5 | (rev) << 2 | (patch)) | ||
137 | |||
138 | /* | ||
128 | * FPU implementation/revision register (CP1 control register 0). | 139 | * FPU implementation/revision register (CP1 control register 0). |
129 | * | 140 | * |
130 | * +---------------------------------+----------------+----------------+ | 141 | * +---------------------------------+----------------+----------------+ |
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 9985cb7c16e7..89c81922d47c 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h | |||
@@ -534,6 +534,8 @@ | |||
534 | #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) | 534 | #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) |
535 | #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) | 535 | #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) |
536 | 536 | ||
537 | #define MIPS_CONF7_WII (_ULCAST_(1) << 31) | ||
538 | |||
537 | /* | 539 | /* |
538 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. | 540 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. |
539 | */ | 541 | */ |
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 13a3502eef44..ec0eeebd8802 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h | |||
@@ -177,18 +177,22 @@ | |||
177 | #endif | 177 | #endif |
178 | 178 | ||
179 | /* | 179 | /* |
180 | * The RM9000 has a bug (though PMC-Sierra opposes it being called that) | 180 | * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra |
181 | * where invalid instructions in the same I-cache line worth of instructions | 181 | * opposes it being called that) where invalid instructions in the same |
182 | * being fetched may case spurious exceptions. | 182 | * I-cache line worth of instructions being fetched may case spurious |
183 | */ | 183 | * exceptions. |
184 | #if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ | 184 | */ |
185 | defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) | 185 | #if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MOMENCO_JAGUAR_ATX) || \ |
186 | defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) || \ | ||
187 | defined(CONFIG_MOMENCO_OCELOT) || defined(CONFIG_MOMENCO_OCELOT_3) || \ | ||
188 | defined(CONFIG_MOMENCO_OCELOT_C) || defined(CONFIG_PMC_YOSEMITE) || \ | ||
189 | defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC) | ||
186 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 | 190 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 |
187 | #endif | 191 | #endif |
188 | 192 | ||
189 | 193 | ||
190 | /* | 194 | /* |
191 | * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that | 195 | * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that |
192 | * may cause ll / sc and lld / scd sequences to execute non-atomically. | 196 | * may cause ll / sc and lld / scd sequences to execute non-atomically. |
193 | */ | 197 | */ |
194 | #ifdef CONFIG_SGI_IP27 | 198 | #ifdef CONFIG_SGI_IP27 |