diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2012-10-17 07:09:54 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-17 15:06:59 -0400 |
commit | d7d4eeddb8f72342f70621c4b3cb718af9361712 (patch) | |
tree | e8a11c37fa8dbaf9e93859e91812ff131ca0e20b /include | |
parent | 76e438303403f301f3509479b544e41518edd059 (diff) |
drm/i915: Allow DRM_ROOT_ONLY|DRM_MASTER to submit privileged batchbuffers
With the introduction of per-process GTT space, the hardware designers
thought it wise to also limit the ability to write to MMIO space to only
a "secure" batch buffer. The ability to rewrite registers is the only
way to program the hardware to perform certain operations like scanline
waits (required for tear-free windowed updates). So we either have a
choice of adding an interface to perform those synchronized updates
inside the kernel, or we permit certain processes the ability to write
to the "safe" registers from within its command stream. This patch
exposes the ability to submit a SECURE batch buffer to
DRM_ROOT_ONLY|DRM_MASTER processes.
v2: Haswell split up bit8 into a ppgtt bit (still bit8) and a security
bit (bit 13, accidentally not set). Also add a comment explaining why
secure batches need a global gtt binding.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> (v1)
[danvet: added hsw fixup.]
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'include')
-rw-r--r-- | include/drm/i915_drm.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index c8833009f37b..0e6e135f5397 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h | |||
@@ -314,6 +314,7 @@ typedef struct drm_i915_irq_wait { | |||
314 | #define I915_PARAM_HAS_SEMAPHORES 20 | 314 | #define I915_PARAM_HAS_SEMAPHORES 20 |
315 | #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 | 315 | #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 |
316 | #define I915_PARAM_RSVD_FOR_FUTURE_USE 22 | 316 | #define I915_PARAM_RSVD_FOR_FUTURE_USE 22 |
317 | #define I915_PARAM_HAS_SECURE_BATCHES 23 | ||
317 | 318 | ||
318 | typedef struct drm_i915_getparam { | 319 | typedef struct drm_i915_getparam { |
319 | int param; | 320 | int param; |
@@ -679,6 +680,11 @@ struct drm_i915_gem_execbuffer2 { | |||
679 | /** Resets the SO write offset registers for transform feedback on gen7. */ | 680 | /** Resets the SO write offset registers for transform feedback on gen7. */ |
680 | #define I915_EXEC_GEN7_SOL_RESET (1<<8) | 681 | #define I915_EXEC_GEN7_SOL_RESET (1<<8) |
681 | 682 | ||
683 | /** Request a privileged ("secure") batch buffer. Note only available for | ||
684 | * DRM_ROOT_ONLY | DRM_MASTER processes. | ||
685 | */ | ||
686 | #define I915_EXEC_SECURE (1<<9) | ||
687 | |||
682 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) | 688 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
683 | #define i915_execbuffer2_set_context_id(eb2, context) \ | 689 | #define i915_execbuffer2_set_context_id(eb2, context) \ |
684 | (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK | 690 | (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK |