Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Arnd Bergmann:
 "New and updated SoC support.  Among the things new for this release
  are:

   - at91: Added support for the new SAMA5D4 SoC, following the earlier
     SAMA5D3
   - bcm: Added support for BCM63XX family of DSL SoCs
   - hisi: Added support for HiP04 server-class SoC
   - meson: Initial support for the Amlogic Meson6 (aka 8726MX) platform
   - shmobile: added support for new r8a7794 (R-Car E2) automotive SoC

  Noteworthy changes to existing SoC support are:

   - imx: convert i.MX1 to device tree
   - omap: lots of power management work
   - omap: base support to enable moving to standard UART driver
   - shmobile: lots of progress for multiplatform support, still
     ongoing"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (171 commits)
  ARM: hisi: depend on ARCH_MULTI_V7
  CNS3xxx: Fix debug UART.
  ARM: at91: fix nommu build regression
  ARM: meson: add basic support for MesonX SoCs
  ARM: meson: debug: add debug UART for earlyprintk support
  irq: Export handle_fasteoi_irq
  ARM: mediatek: Add earlyprintk support for mt6589
  ARM: hisi: Fix platmcpm compilation when ARMv6 is selected
  ARM: debug: fix alphanumerical order on debug uarts
  ARM: at91: document Atmel SMART compatibles
  ARM: at91: add sama5d4 support to sama5_defconfig
  ARM: at91: dt: add device tree file for SAMA5D4ek board
  ARM: at91: dt: add device tree file for SAMA5D4 SoC
  ARM: at91: SAMA5D4 SoC detection code and low level routines
  ARM: at91: introduce basic SAMA5D4 support
  clk: at91: add a driver for the h32mx clock
  ARM: pxa3xx: provide specific platform_devices for all ssp ports
  ARM: pxa: ssp: provide platform_device_id for PXA3xx
  ARM: OMAP4+: Remove static iotable mappings for SRAM
  ARM: OMAP4+: Move SRAM data to DT
  ...

7 files changed, 167 insertions, 40 deletions

diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index 654151e24288..ddaef8620b2c 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -128,7 +128,7 @@
 #define IMX6Q_CLK_ECSPI5                        116
 #define IMX6DL_CLK_I2C4                         116
 #define IMX6QDL_CLK_ENET                        117
-#define IMX6QDL_CLK_ESAI                        118
+#define IMX6QDL_CLK_ESAI_EXTAL                  118
 #define IMX6QDL_CLK_GPT_IPG                     119
 #define IMX6QDL_CLK_GPT_IPG_PER                 120
 #define IMX6QDL_CLK_GPU2D_CORE                  121
@@ -218,7 +218,36 @@
 #define IMX6QDL_CLK_LVDS2_SEL                   205
 #define IMX6QDL_CLK_LVDS1_GATE                  206
 #define IMX6QDL_CLK_LVDS2_GATE                  207
-#define IMX6QDL_CLK_ESAI_AHB                    208
-#define IMX6QDL_CLK_END                         209
+#define IMX6QDL_CLK_ESAI_IPG                    208
+#define IMX6QDL_CLK_ESAI_MEM                    209
+#define IMX6QDL_CLK_ASRC_IPG                    210
+#define IMX6QDL_CLK_ASRC_MEM                    211
+#define IMX6QDL_CLK_LVDS1_IN                    212
+#define IMX6QDL_CLK_LVDS2_IN                    213
+#define IMX6QDL_CLK_ANACLK1                     214
+#define IMX6QDL_CLK_ANACLK2                     215
+#define IMX6QDL_PLL1_BYPASS_SRC                 216
+#define IMX6QDL_PLL2_BYPASS_SRC                 217
+#define IMX6QDL_PLL3_BYPASS_SRC                 218
+#define IMX6QDL_PLL4_BYPASS_SRC                 219
+#define IMX6QDL_PLL5_BYPASS_SRC                 220
+#define IMX6QDL_PLL6_BYPASS_SRC                 221
+#define IMX6QDL_PLL7_BYPASS_SRC                 222
+#define IMX6QDL_CLK_PLL1                        223
+#define IMX6QDL_CLK_PLL2                        224
+#define IMX6QDL_CLK_PLL3                        225
+#define IMX6QDL_CLK_PLL4                        226
+#define IMX6QDL_CLK_PLL5                        227
+#define IMX6QDL_CLK_PLL6                        228
+#define IMX6QDL_CLK_PLL7                        229
+#define IMX6QDL_PLL1_BYPASS                     230
+#define IMX6QDL_PLL2_BYPASS                     231
+#define IMX6QDL_PLL3_BYPASS                     232
+#define IMX6QDL_PLL4_BYPASS                     233
+#define IMX6QDL_PLL5_BYPASS                     234
+#define IMX6QDL_PLL6_BYPASS                     235
+#define IMX6QDL_PLL7_BYPASS                     236
+#define IMX6QDL_CLK_GPT_3M                      237
+#define IMX6QDL_CLK_END                         238
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
index b91dd462ba85..9ce4e421096f 100644
--- a/include/dt-bindings/clock/imx6sl-clock.h
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -146,6 +146,34 @@
 #define IMX6SL_CLK_PLL4_AUDIO_DIV       133
 #define IMX6SL_CLK_SPBA                 134
 #define IMX6SL_CLK_ENET                 135
-#define IMX6SL_CLK_END                  136
+#define IMX6SL_CLK_LVDS1_SEL            136
+#define IMX6SL_CLK_LVDS1_OUT            137
+#define IMX6SL_CLK_LVDS1_IN             138
+#define IMX6SL_CLK_ANACLK1              139
+#define IMX6SL_PLL1_BYPASS_SRC          140
+#define IMX6SL_PLL2_BYPASS_SRC          141
+#define IMX6SL_PLL3_BYPASS_SRC          142
+#define IMX6SL_PLL4_BYPASS_SRC          143
+#define IMX6SL_PLL5_BYPASS_SRC          144
+#define IMX6SL_PLL6_BYPASS_SRC          145
+#define IMX6SL_PLL7_BYPASS_SRC          146
+#define IMX6SL_CLK_PLL1                 147
+#define IMX6SL_CLK_PLL2                 148
+#define IMX6SL_CLK_PLL3                 149
+#define IMX6SL_CLK_PLL4                 150
+#define IMX6SL_CLK_PLL5                 151
+#define IMX6SL_CLK_PLL6                 152
+#define IMX6SL_CLK_PLL7                 153
+#define IMX6SL_PLL1_BYPASS              154
+#define IMX6SL_PLL2_BYPASS              155
+#define IMX6SL_PLL3_BYPASS              156
+#define IMX6SL_PLL4_BYPASS              157
+#define IMX6SL_PLL5_BYPASS              158
+#define IMX6SL_PLL6_BYPASS              159
+#define IMX6SL_PLL7_BYPASS              160
+#define IMX6SL_CLK_SSI1_IPG             161
+#define IMX6SL_CLK_SSI2_IPG             162
+#define IMX6SL_CLK_SSI3_IPG             163
+#define IMX6SL_CLK_END                  164
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
index 421d8bb76f2f..995709119ec5 100644
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -251,6 +251,29 @@
 #define IMX6SX_CLK_SAI2_IPG             238
 #define IMX6SX_CLK_ESAI_IPG             239
 #define IMX6SX_CLK_ESAI_MEM             240
-#define IMX6SX_CLK_CLK_END              241
+#define IMX6SX_CLK_LVDS1_IN             241
+#define IMX6SX_CLK_ANACLK1              242
+#define IMX6SX_PLL1_BYPASS_SRC          243
+#define IMX6SX_PLL2_BYPASS_SRC          244
+#define IMX6SX_PLL3_BYPASS_SRC          245
+#define IMX6SX_PLL4_BYPASS_SRC          246
+#define IMX6SX_PLL5_BYPASS_SRC          247
+#define IMX6SX_PLL6_BYPASS_SRC          248
+#define IMX6SX_PLL7_BYPASS_SRC          249
+#define IMX6SX_CLK_PLL1                 250
+#define IMX6SX_CLK_PLL2                 251
+#define IMX6SX_CLK_PLL3                 252
+#define IMX6SX_CLK_PLL4                 253
+#define IMX6SX_CLK_PLL5                 254
+#define IMX6SX_CLK_PLL6                 255
+#define IMX6SX_CLK_PLL7                 256
+#define IMX6SX_PLL1_BYPASS              257
+#define IMX6SX_PLL2_BYPASS              258
+#define IMX6SX_PLL3_BYPASS              259
+#define IMX6SX_PLL4_BYPASS              260
+#define IMX6SX_PLL5_BYPASS              261
+#define IMX6SX_PLL6_BYPASS              262
+#define IMX6SX_PLL7_BYPASS              263
+#define IMX6SX_CLK_CLK_END              264
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
diff --git a/include/dt-bindings/clock/r8a7740-clock.h b/include/dt-bindings/clock/r8a7740-clock.h
new file mode 100644
index 000000000000..f6b4b0fe7a43
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7740-clock.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2014 Ulrich Hecht
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__
+#define __DT_BINDINGS_CLOCK_R8A7740_H__
+
+/* CPG */
+#define R8A7740_CLK_SYSTEM      0
+#define R8A7740_CLK_PLLC0       1
+#define R8A7740_CLK_PLLC1       2
+#define R8A7740_CLK_PLLC2       3
+#define R8A7740_CLK_R           4
+#define R8A7740_CLK_USB24S      5
+#define R8A7740_CLK_I           6
+#define R8A7740_CLK_ZG          7
+#define R8A7740_CLK_B           8
+#define R8A7740_CLK_M1          9
+#define R8A7740_CLK_HP          10
+#define R8A7740_CLK_HPP         11
+#define R8A7740_CLK_USBP        12
+#define R8A7740_CLK_S           13
+#define R8A7740_CLK_ZB          14
+#define R8A7740_CLK_M3          15
+#define R8A7740_CLK_CP          16
+
+/* MSTP1 */
+#define R8A7740_CLK_CEU21       28
+#define R8A7740_CLK_CEU20       27
+#define R8A7740_CLK_TMU0        25
+#define R8A7740_CLK_LCDC1       17
+#define R8A7740_CLK_IIC0        16
+#define R8A7740_CLK_TMU1        11
+#define R8A7740_CLK_LCDC0       0
+
+/* MSTP2 */
+#define R8A7740_CLK_SCIFA6      30
+#define R8A7740_CLK_SCIFA7      22
+#define R8A7740_CLK_DMAC1       18
+#define R8A7740_CLK_DMAC2       17
+#define R8A7740_CLK_DMAC3       16
+#define R8A7740_CLK_USBDMAC     14
+#define R8A7740_CLK_SCIFA5      7
+#define R8A7740_CLK_SCIFB       6
+#define R8A7740_CLK_SCIFA0      4
+#define R8A7740_CLK_SCIFA1      3
+#define R8A7740_CLK_SCIFA2      2
+#define R8A7740_CLK_SCIFA3      1
+#define R8A7740_CLK_SCIFA4      0
+
+/* MSTP3 */
+#define R8A7740_CLK_CMT1        29
+#define R8A7740_CLK_FSI         28
+#define R8A7740_CLK_IIC1        23
+#define R8A7740_CLK_USBF        20
+#define R8A7740_CLK_SDHI0       14
+#define R8A7740_CLK_SDHI1       13
+#define R8A7740_CLK_MMC         12
+#define R8A7740_CLK_GETHER      9
+#define R8A7740_CLK_TPU0        4
+
+/* MSTP4 */
+#define R8A7740_CLK_USBH        16
+#define R8A7740_CLK_SDHI2       15
+#define R8A7740_CLK_USBFUNC     7
+#define R8A7740_CLK_USBPHY      6
+
+/* SUBCK* */
+#define R8A7740_CLK_SUBCK       9
+#define R8A7740_CLK_SUBCK2      10
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 00953d9484cb..d6b56b21539b 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -166,6 +166,9 @@
 #define VF610_CLK_DMAMUX3               153
 #define VF610_CLK_FLEXCAN0_EN           154
 #define VF610_CLK_FLEXCAN1_EN           155
-#define VF610_CLK_END                   156
+#define VF610_CLK_PLL7_MAIN             156
+#define VF610_CLK_USBPHY0               157
+#define VF610_CLK_USBPHY1               158
+#define VF610_CLK_END                   159
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index de4268d4987a..c8e3b3d1eded 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -125,6 +125,7 @@ extern void __iomem *at91_pmc_base;
 #define         AT91_PMC_PLLADIV2       (1 << 12)               /* PLLA divisor by 2 [some SAM9 only] */
 #define                 AT91_PMC_PLLADIV2_OFF           (0 << 12)
 #define                 AT91_PMC_PLLADIV2_ON            (1 << 12)
+#define         AT91_PMC_H32MXDIV       BIT(24)
 
 #define AT91_PMC_USB            0x38                    /* USB Clock Register [some SAM9 only] */
 #define         AT91_PMC_USBS           (0x1 <<  0)             /* USB OHCI Input clock selection */
diff --git a/include/linux/platform_data/tegra_emc.h b/include/linux/platform_data/tegra_emc.h
deleted file mode 100644
index df67505e98f8..000000000000
--- a/include/linux/platform_data/tegra_emc.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (C) 2011 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@android.com>
- *      Olof Johansson <olof@lixom.net>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __TEGRA_EMC_H_
-#define __TEGRA_EMC_H_
-
-#define TEGRA_EMC_NUM_REGS 46
-
-struct tegra_emc_table {
-        unsigned long rate;
-        u32 regs[TEGRA_EMC_NUM_REGS];
-};
-
-struct tegra_emc_pdata {
-        int num_tables;
-        struct tegra_emc_table *tables;
-};
-
-#endif