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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-12-06 12:43:26 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-12-06 12:43:26 -0500
commitceaeee6ad6c2a24bf37d9f426414cf3007432352 (patch)
treefa330133773d10a9d7f329e3db2cc371999c6d86 /include
parent3743d33edf4e49376384822c57c4ee5cdf2d32f8 (diff)
parent5e2862eb5a263a0339a85545d96fb20995d67b1f (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Oprofile: Fix computation of number of counters. [MIPS] Alchemy: fix IRQ bases [MIPS] Alchemy: replace ffs() with __ffs() [MIPS] BCM1480: Fix interrupt routing, take 2.
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h21
1 files changed, 11 insertions, 10 deletions
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 3bdce9126f16..bf7701243d71 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -526,7 +526,7 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
526/* Au1000 */ 526/* Au1000 */
527#ifdef CONFIG_SOC_AU1000 527#ifdef CONFIG_SOC_AU1000
528enum soc_au1000_ints { 528enum soc_au1000_ints {
529 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE, 529 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
530 AU1000_UART0_INT = AU1000_FIRST_INT, 530 AU1000_UART0_INT = AU1000_FIRST_INT,
531 AU1000_UART1_INT, /* au1000 */ 531 AU1000_UART1_INT, /* au1000 */
532 AU1000_UART2_INT, /* au1000 */ 532 AU1000_UART2_INT, /* au1000 */
@@ -605,7 +605,7 @@ enum soc_au1000_ints {
605/* Au1500 */ 605/* Au1500 */
606#ifdef CONFIG_SOC_AU1500 606#ifdef CONFIG_SOC_AU1500
607enum soc_au1500_ints { 607enum soc_au1500_ints {
608 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE, 608 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
609 AU1500_UART0_INT = AU1500_FIRST_INT, 609 AU1500_UART0_INT = AU1500_FIRST_INT,
610 AU1000_PCI_INTA, /* au1500 */ 610 AU1000_PCI_INTA, /* au1500 */
611 AU1000_PCI_INTB, /* au1500 */ 611 AU1000_PCI_INTB, /* au1500 */
@@ -686,7 +686,7 @@ enum soc_au1500_ints {
686/* Au1100 */ 686/* Au1100 */
687#ifdef CONFIG_SOC_AU1100 687#ifdef CONFIG_SOC_AU1100
688enum soc_au1100_ints { 688enum soc_au1100_ints {
689 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE, 689 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
690 AU1100_UART0_INT, 690 AU1100_UART0_INT,
691 AU1100_UART1_INT, 691 AU1100_UART1_INT,
692 AU1100_SD_INT, 692 AU1100_SD_INT,
@@ -761,7 +761,7 @@ enum soc_au1100_ints {
761 761
762#ifdef CONFIG_SOC_AU1550 762#ifdef CONFIG_SOC_AU1550
763enum soc_au1550_ints { 763enum soc_au1550_ints {
764 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE, 764 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
765 AU1550_UART0_INT = AU1550_FIRST_INT, 765 AU1550_UART0_INT = AU1550_FIRST_INT,
766 AU1550_PCI_INTA, 766 AU1550_PCI_INTA,
767 AU1550_PCI_INTB, 767 AU1550_PCI_INTB,
@@ -851,7 +851,7 @@ enum soc_au1550_ints {
851 851
852#ifdef CONFIG_SOC_AU1200 852#ifdef CONFIG_SOC_AU1200
853enum soc_au1200_ints { 853enum soc_au1200_ints {
854 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE, 854 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
855 AU1200_UART0_INT = AU1200_FIRST_INT, 855 AU1200_UART0_INT = AU1200_FIRST_INT,
856 AU1200_SWT_INT, 856 AU1200_SWT_INT,
857 AU1200_SD_INT, 857 AU1200_SD_INT,
@@ -948,11 +948,12 @@ enum soc_au1200_ints {
948 948
949#endif /* CONFIG_SOC_AU1200 */ 949#endif /* CONFIG_SOC_AU1200 */
950 950
951#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 0) 951#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
952#define AU1000_INTC0_INT_LAST (MIPS_CPU_IRQ_BASE + 31) 952#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
953#define AU1000_INTC1_INT_BASE (MIPS_CPU_IRQ_BASE + 32) 953#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
954#define AU1000_INTC1_INT_LAST (MIPS_CPU_IRQ_BASE + 63) 954#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
955#define AU1000_MAX_INTR (MIPS_CPU_IRQ_BASE + 63) 955
956#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
956#define INTX 0xFF /* not valid */ 957#define INTX 0xFF /* not valid */
957 958
958/* Programmable Counters 0 and 1 */ 959/* Programmable Counters 0 and 1 */