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authorSeth Heasley <seth.heasley@intel.com>2010-10-04 16:27:14 -0400
committerJesse Barnes <jbarnes@virtuousgeek.org>2010-10-17 23:03:04 -0400
commitcb04e95bdd0bfd618ab731c84a3ab56b56974df8 (patch)
treeb2af7c9239b2ce4861b5590df684256d71a54d49 /include
parent350a55e9ff6005032407d3234af800f413b03af5 (diff)
PCI: update Intel chipset names and defines
This patch updates the defines for Intel devices in include/linux/pci_ids.h, referenced in arch/x86/pci/irq.c and drivers/i2c/busses/i2c-i801.c, reflecting approved legal branding, and using fuller code-names for products under development. Acked-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'include')
-rw-r--r--include/linux/pci_ids.h18
1 files changed, 9 insertions, 9 deletions
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ea5a3d19aaba..bb6daa5f8240 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2435,10 +2435,10 @@
2435#define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21 2435#define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21
2436#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 2436#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30
2437#define PCI_DEVICE_ID_INTEL_IOAT 0x1a38 2437#define PCI_DEVICE_ID_INTEL_IOAT 0x1a38
2438#define PCI_DEVICE_ID_INTEL_CPT_SMBUS 0x1c22 2438#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
2439#define PCI_DEVICE_ID_INTEL_CPT_LPC_MIN 0x1c41 2439#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
2440#define PCI_DEVICE_ID_INTEL_CPT_LPC_MAX 0x1c5f 2440#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
2441#define PCI_DEVICE_ID_INTEL_PBG_LPC 0x1d40 2441#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC 0x1d40
2442#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 2442#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410
2443#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411 2443#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411
2444#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413 2444#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413
@@ -2644,9 +2644,9 @@
2644#define PCI_DEVICE_ID_INTEL_ICH10_3 0x3a1a 2644#define PCI_DEVICE_ID_INTEL_ICH10_3 0x3a1a
2645#define PCI_DEVICE_ID_INTEL_ICH10_4 0x3a30 2645#define PCI_DEVICE_ID_INTEL_ICH10_4 0x3a30
2646#define PCI_DEVICE_ID_INTEL_ICH10_5 0x3a60 2646#define PCI_DEVICE_ID_INTEL_ICH10_5 0x3a60
2647#define PCI_DEVICE_ID_INTEL_PCH_LPC_MIN 0x3b00 2647#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN 0x3b00
2648#define PCI_DEVICE_ID_INTEL_PCH_LPC_MAX 0x3b1f 2648#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX 0x3b1f
2649#define PCI_DEVICE_ID_INTEL_PCH_SMBUS 0x3b30 2649#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
2650#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f 2650#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
2651#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0 2651#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
2652#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5 2652#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5
@@ -2655,8 +2655,8 @@
2655#define PCI_DEVICE_ID_INTEL_5400_FBD0 0x4035 2655#define PCI_DEVICE_ID_INTEL_5400_FBD0 0x4035
2656#define PCI_DEVICE_ID_INTEL_5400_FBD1 0x4036 2656#define PCI_DEVICE_ID_INTEL_5400_FBD1 0x4036
2657#define PCI_DEVICE_ID_INTEL_IOAT_SCNB 0x65ff 2657#define PCI_DEVICE_ID_INTEL_IOAT_SCNB 0x65ff
2658#define PCI_DEVICE_ID_INTEL_TOLAPAI_0 0x5031 2658#define PCI_DEVICE_ID_INTEL_EP80579_0 0x5031
2659#define PCI_DEVICE_ID_INTEL_TOLAPAI_1 0x5032 2659#define PCI_DEVICE_ID_INTEL_EP80579_1 0x5032
2660#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 2660#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
2661#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 2661#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
2662#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 2662#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020