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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-01-30 11:29:05 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-01-30 11:29:05 -0500
commitc9cc8e771cb62e495765793e4b7d06016ae1b525 (patch)
tree42c3ae364cd8b22e3263403f0baa2b5e8070b5da /include
parent59df3230fc57fa8900bebf3d2d68221d549f3c7c (diff)
parentb9d1902cd281d9b829fb3d6ee9148d28c8c63382 (diff)
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 4117/1: S3C2412: Fix writel() usage in selection code [ARM] 4111/1: Allow VFP to work with thread migration on SMP [ARM] 4112/1: Only ioremap to supersections if DOMAIN_IO is zero [ARM] 4106/1: S3C2410: typo fixes in register definitions [ARM] 4102/1: Allow for PHYS_OFFSET on any valid 2MiB address [ARM] Fix AMBA serial drivers for non-first serial ports [ARM] 4100/1: iop3xx: fix cpu mask for iop333 [ARM] Update mach-types [ARM] Fix show_mem() for discontigmem [ARM] 4096/1: S3C24XX: change return code form s3c2410_gpio_getcfg() [ARM] 4095/1: S3C24XX: Fix GPIO set for Bank A [ARM] 4092/1: i.MX/MX1 CPU Frequency scaling latency definition [ARM] 4089/1: AT91: GPIO wake IRQ cleanup [ARM] 4088/1: AT91: Unbalanced IRQ in serial driver suspend/resume [ARM] 4087/1: AT91: CPU reset for SAM9x processors [ARM] 4086/1: AT91: Whitespace cleanup [ARM] 4085/1: AT91: Header fixes. [ARM] 4084/1: Remove CONFIG_DEBUG_WAITQ
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_ecc.h8
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_pmc.h2
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_rstc.h2
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_rtc.h16
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200.h2
-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h2
-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h6
-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam926x_mc.h16
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h4
-rw-r--r--include/asm-arm/arch-s3c2410/regs-mem.h14
-rw-r--r--include/asm-arm/fpstate.h3
11 files changed, 39 insertions, 36 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91_ecc.h b/include/asm-arm/arch-at91rm9200/at91_ecc.h
index fddf256a98d3..5c564ede5c5d 100644
--- a/include/asm-arm/arch-at91rm9200/at91_ecc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_ecc.h
@@ -14,7 +14,7 @@
14#define AT91_ECC_H 14#define AT91_ECC_H
15 15
16#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */ 16#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */
17#define AT91_ECC_RST (1 << 0) /* Reset parity */ 17#define AT91_ECC_RST (1 << 0) /* Reset parity */
18 18
19#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */ 19#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */
20#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */ 20#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */
@@ -23,16 +23,16 @@
23#define AT91_ECC_PAGESIZE_2112 (2) 23#define AT91_ECC_PAGESIZE_2112 (2)
24#define AT91_ECC_PAGESIZE_4224 (3) 24#define AT91_ECC_PAGESIZE_4224 (3)
25 25
26#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */ 26#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */
27#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */ 27#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */
28#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ 28#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
29#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */ 29#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */
30 30
31#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */ 31#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */
32#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */ 32#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */
33#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ 33#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
34 34
35#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */ 35#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */
36#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */ 36#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */
37 37
38#endif 38#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_pmc.h b/include/asm-arm/arch-at91rm9200/at91_pmc.h
index de8c3da74a01..c3b489d09b6c 100644
--- a/include/asm-arm/arch-at91rm9200/at91_pmc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_pmc.h
@@ -61,7 +61,7 @@
61#define AT91_PMC_CSS_PLLA (2 << 0) 61#define AT91_PMC_CSS_PLLA (2 << 0)
62#define AT91_PMC_CSS_PLLB (3 << 0) 62#define AT91_PMC_CSS_PLLB (3 << 0)
63#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ 63#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
64#define AT91_PMC_PRES_1 (0 << 2) 64#define AT91_PMC_PRES_1 (0 << 2)
65#define AT91_PMC_PRES_2 (1 << 2) 65#define AT91_PMC_PRES_2 (1 << 2)
66#define AT91_PMC_PRES_4 (2 << 2) 66#define AT91_PMC_PRES_4 (2 << 2)
67#define AT91_PMC_PRES_8 (3 << 2) 67#define AT91_PMC_PRES_8 (3 << 2)
diff --git a/include/asm-arm/arch-at91rm9200/at91_rstc.h b/include/asm-arm/arch-at91rm9200/at91_rstc.h
index ccdc52da973d..237d3c40b318 100644
--- a/include/asm-arm/arch-at91rm9200/at91_rstc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_rstc.h
@@ -17,7 +17,7 @@
17#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ 17#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
18#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ 18#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
19#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ 19#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
20#define AT01_RSTC_KEY (0xff << 24) /* KEY Password */ 20#define AT91_RSTC_KEY (0xff << 24) /* KEY Password */
21 21
22#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ 22#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
23#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ 23#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
diff --git a/include/asm-arm/arch-at91rm9200/at91_rtc.h b/include/asm-arm/arch-at91rm9200/at91_rtc.h
index 6e5065d56260..095fe0883102 100644
--- a/include/asm-arm/arch-at91rm9200/at91_rtc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_rtc.h
@@ -21,21 +21,21 @@
21#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ 21#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
22#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ 22#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
23#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) 23#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
24#define AT91_RTC_TIMEVSEL_HOUR (1 << 8) 24#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
25#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) 25#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
26#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) 26#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
27#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ 27#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
28#define AT91_RTC_CALEVSEL_WEEK (0 << 16) 28#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
29#define AT91_RTC_CALEVSEL_MONTH (1 << 16) 29#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
30#define AT91_RTC_CALEVSEL_YEAR (2 << 16) 30#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
31 31
32#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ 32#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
33#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ 33#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
34 34
35#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ 35#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
36#define AT91_RTC_SEC (0x7f << 0) /* Current Second */ 36#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
37#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ 37#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
38#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ 38#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
39#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ 39#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
40 40
41#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ 41#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
index 4d51177efddd..c569b6a21a42 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -274,7 +274,7 @@
274#define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */ 274#define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */
275#define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */ 275#define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */
276#define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */ 276#define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */
277#define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */ 277#define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */
278#define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */ 278#define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */
279#define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */ 279#define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */
280#define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */ 280#define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
index 746d973705bf..78f6b4917b8b 100644
--- a/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
+++ b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
@@ -58,7 +58,7 @@
58#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 58#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
59 59
60#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ 60#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
61#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 61#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
62#define AT91_MATRIX_CS1A_SMC (0 << 1) 62#define AT91_MATRIX_CS1A_SMC (0 << 1)
63#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 63#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
64#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ 64#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
index 270a5dcdf1cd..ec88efabbe6c 100644
--- a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
+++ b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
@@ -15,7 +15,7 @@
15 15
16#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ 16#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */
17#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 17#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
18#define AT01_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 18#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
19 19
20#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ 20#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */
21#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ 21#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */
@@ -43,8 +43,8 @@
43 43
44#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ 44#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
45#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 45#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
46#define AT91_MATRIX_CS1A_SMC (0 << 1) 46#define AT91_MATRIX_CS1A_SMC (0 << 1)
47#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 47#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
48#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ 48#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
49#define AT91_MATRIX_CS3A_SMC (0 << 3) 49#define AT91_MATRIX_CS3A_SMC (0 << 3)
50#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) 50#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
diff --git a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
index 7d94968b5d57..972e7531c7f4 100644
--- a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
+++ b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
@@ -33,14 +33,14 @@
33#define AT91_SDRAMC_NC_9 (1 << 0) 33#define AT91_SDRAMC_NC_9 (1 << 0)
34#define AT91_SDRAMC_NC_10 (2 << 0) 34#define AT91_SDRAMC_NC_10 (2 << 0)
35#define AT91_SDRAMC_NC_11 (3 << 0) 35#define AT91_SDRAMC_NC_11 (3 << 0)
36#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ 36#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
37#define AT91_SDRAMC_NR_11 (0 << 2) 37#define AT91_SDRAMC_NR_11 (0 << 2)
38#define AT91_SDRAMC_NR_12 (1 << 2) 38#define AT91_SDRAMC_NR_12 (1 << 2)
39#define AT91_SDRAMC_NR_13 (2 << 2) 39#define AT91_SDRAMC_NR_13 (2 << 2)
40#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ 40#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
41#define AT91_SDRAMC_NB_2 (0 << 4) 41#define AT91_SDRAMC_NB_2 (0 << 4)
42#define AT91_SDRAMC_NB_4 (1 << 4) 42#define AT91_SDRAMC_NB_4 (1 << 4)
43#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ 43#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
44#define AT91_SDRAMC_CAS_1 (1 << 5) 44#define AT91_SDRAMC_CAS_1 (1 << 5)
45#define AT91_SDRAMC_CAS_2 (2 << 5) 45#define AT91_SDRAMC_CAS_2 (2 << 5)
46#define AT91_SDRAMC_CAS_3 (3 << 5) 46#define AT91_SDRAMC_CAS_3 (3 << 5)
@@ -110,10 +110,10 @@
110#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ 110#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
111#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ 111#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
112#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ 112#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
113#define AT91_SMC_EXNWMODE (3 << 5) /* NWAIT Mode */ 113#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
114#define AT91_SMC_EXNWMODE_DISABLE (0 << 5) 114#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
115#define AT91_SMC_EXNWMODE_FROZEN (2 << 5) 115#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
116#define AT91_SMC_EXNWMODE_READY (3 << 5) 116#define AT91_SMC_EXNWMODE_READY (3 << 4)
117#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ 117#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
118#define AT91_SMC_BAT_SELECT (0 << 8) 118#define AT91_SMC_BAT_SELECT (0 << 8)
119#define AT91_SMC_BAT_WRITE (1 << 8) 119#define AT91_SMC_BAT_WRITE (1 << 8)
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index b2893e32a236..eae91694edcd 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -52,10 +52,10 @@
52/* general configuration options */ 52/* general configuration options */
53 53
54#define S3C2410_GPIO_LEAVE (0xFFFFFFFF) 54#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
55#define S3C2410_GPIO_INPUT (0xFFFFFFF0) 55#define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */
56#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1) 56#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1)
57#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */ 57#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */
58#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */ 58#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */
59#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ 59#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
60 60
61/* register address for the GPIO registers. 61/* register address for the GPIO registers.
diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
index 375dca50364e..e4d82341f7ba 100644
--- a/include/asm-arm/arch-s3c2410/regs-mem.h
+++ b/include/asm-arm/arch-s3c2410/regs-mem.h
@@ -133,10 +133,10 @@
133#define S3C2410_BANKCON_SDRAM (0x3 << 15) 133#define S3C2410_BANKCON_SDRAM (0x3 << 15)
134 134
135/* next bits only for EDO DRAM in 6,7 */ 135/* next bits only for EDO DRAM in 6,7 */
136#define S3C2400_BANKCON_EDO_Trdc1 (0x00 << 4) 136#define S3C2400_BANKCON_EDO_Trcd1 (0x00 << 4)
137#define S3C2400_BANKCON_EDO_Trdc2 (0x01 << 4) 137#define S3C2400_BANKCON_EDO_Trcd2 (0x01 << 4)
138#define S3C2400_BANKCON_EDO_Trdc3 (0x02 << 4) 138#define S3C2400_BANKCON_EDO_Trcd3 (0x02 << 4)
139#define S3C2400_BANKCON_EDO_Trdc4 (0x03 << 4) 139#define S3C2400_BANKCON_EDO_Trcd4 (0x03 << 4)
140 140
141/* CAS pulse width */ 141/* CAS pulse width */
142#define S3C2400_BANKCON_EDO_PULSE1 (0x00 << 3) 142#define S3C2400_BANKCON_EDO_PULSE1 (0x00 << 3)
@@ -153,9 +153,9 @@
153#define S3C2400_BANKCON_EDO_SCANb11 (0x03 << 0) 153#define S3C2400_BANKCON_EDO_SCANb11 (0x03 << 0)
154 154
155/* next bits only for SDRAM in 6,7 */ 155/* next bits only for SDRAM in 6,7 */
156#define S3C2410_BANKCON_Trdc2 (0x00 << 2) 156#define S3C2410_BANKCON_Trcd2 (0x00 << 2)
157#define S3C2410_BANKCON_Trdc3 (0x01 << 2) 157#define S3C2410_BANKCON_Trcd3 (0x01 << 2)
158#define S3C2410_BANKCON_Trdc4 (0x02 << 2) 158#define S3C2410_BANKCON_Trcd4 (0x02 << 2)
159 159
160/* control column address select */ 160/* control column address select */
161#define S3C2410_BANKCON_SCANb8 (0x00 << 0) 161#define S3C2410_BANKCON_SCANb8 (0x00 << 0)
diff --git a/include/asm-arm/fpstate.h b/include/asm-arm/fpstate.h
index 6af4e6bd1290..f31cda5a55ee 100644
--- a/include/asm-arm/fpstate.h
+++ b/include/asm-arm/fpstate.h
@@ -35,6 +35,9 @@ struct vfp_hard_struct {
35 */ 35 */
36 __u32 fpinst; 36 __u32 fpinst;
37 __u32 fpinst2; 37 __u32 fpinst2;
38#ifdef CONFIG_SMP
39 __u32 cpu;
40#endif
38}; 41};
39 42
40union vfp_state { 43union vfp_state {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 10:59:11 -0500