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authorCatalin Marinas <catalin.marinas@arm.com>2007-11-22 12:32:01 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-01-26 09:41:28 -0500
commitc98929c07a01c9ec2e1e5253456acc7168da8b66 (patch)
tree7d0014de51fe530b95bce7f74d9122229067f850 /include
parent9b73e76f3cf63379dcf45fcd4f112f5812418d0a (diff)
[ARM] 4582/2: Add support for the common VFP subarchitecture
This patch allows the VFP support code to run correctly on CPUs compatible with the common VFP subarchitecture specification (Appendix B in the ARM ARM v7-A and v7-R edition). It implements support for VFP subarchitecture 2 while being backwards compatible with subarchitecture 1. On VFP subarchitecture 1, the arithmetic exceptions are asynchronous (or imprecise as described in the old ARM ARM) unless the FPSCR.IXE bit is 1. The exceptional instructions can be read from FPINST and FPINST2 registers. With VFP subarchitecture 2, the arithmetic exceptions can also be synchronous and marked by the FPEXC.DEX bit (the FPEXC.EX bit is cleared). CPUs implementing the synchronous arithmetic exceptions don't have the FPINST and FPINST2 registers and accessing them would trigger and undefined exception. Note that FPEXC.EX bit has an additional meaning on subarchitecture 1 - if it isn't set, there is no additional information in FPINST and FPINST2 that needs to be saved at context switch or when lazy-loading the VFP state of a different thread. The patch also removes the clearing of the cumulative exception flags in FPSCR when additional exceptions were raised. It is up to the user application to clear these bits. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/vfp.h30
1 files changed, 15 insertions, 15 deletions
diff --git a/include/asm-arm/vfp.h b/include/asm-arm/vfp.h
index bd6be9d7f772..9d474d47b266 100644
--- a/include/asm-arm/vfp.h
+++ b/include/asm-arm/vfp.h
@@ -8,6 +8,8 @@
8#define FPSID cr0 8#define FPSID cr0
9#define FPSCR cr1 9#define FPSCR cr1
10#define FPEXC cr8 10#define FPEXC cr8
11#define FPINST cr9
12#define FPINST2 cr10
11 13
12/* FPSID bits */ 14/* FPSID bits */
13#define FPSID_IMPLEMENTER_BIT (24) 15#define FPSID_IMPLEMENTER_BIT (24)
@@ -28,6 +30,19 @@
28/* FPEXC bits */ 30/* FPEXC bits */
29#define FPEXC_EX (1 << 31) 31#define FPEXC_EX (1 << 31)
30#define FPEXC_EN (1 << 30) 32#define FPEXC_EN (1 << 30)
33#define FPEXC_DEX (1 << 29)
34#define FPEXC_FP2V (1 << 28)
35#define FPEXC_VV (1 << 27)
36#define FPEXC_TFV (1 << 26)
37#define FPEXC_LENGTH_BIT (8)
38#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
39#define FPEXC_IDF (1 << 7)
40#define FPEXC_IXF (1 << 4)
41#define FPEXC_UFF (1 << 3)
42#define FPEXC_OFF (1 << 2)
43#define FPEXC_DZF (1 << 1)
44#define FPEXC_IOF (1 << 0)
45#define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
31 46
32/* FPSCR bits */ 47/* FPSCR bits */
33#define FPSCR_DEFAULT_NAN (1<<25) 48#define FPSCR_DEFAULT_NAN (1<<25)
@@ -55,21 +70,6 @@
55#define FPSCR_IXC (1<<4) 70#define FPSCR_IXC (1<<4)
56#define FPSCR_IDC (1<<7) 71#define FPSCR_IDC (1<<7)
57 72
58/*
59 * VFP9-S specific.
60 */
61#define FPINST cr9
62#define FPINST2 cr10
63
64/* FPEXC bits */
65#define FPEXC_FPV2 (1<<28)
66#define FPEXC_LENGTH_BIT (8)
67#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
68#define FPEXC_INV (1 << 7)
69#define FPEXC_UFC (1 << 3)
70#define FPEXC_OFC (1 << 2)
71#define FPEXC_IOC (1 << 0)
72
73/* Bit patterns for decoding the packaged operation descriptors */ 73/* Bit patterns for decoding the packaged operation descriptors */
74#define VFPOPDESC_LENGTH_BIT (9) 74#define VFPOPDESC_LENGTH_BIT (9)
75#define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT) 75#define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT)