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authorOlof Johansson <olof@lixom.net>2014-01-02 13:57:05 -0500
committerOlof Johansson <olof@lixom.net>2014-01-02 13:57:05 -0500
commitc7fed591a6d5ce080482e4237bd02c99857c0d4f (patch)
treef697a76b366a228e21c222061bcef7000b973949 /include
parentefcf3d38f128cfbfc7a62c3a5dc3fb42991c12e5 (diff)
parent20bdcab8268cb05702e12ae9013be96ecc7ec3a6 (diff)
Merge tag 'renesas-sh-sci3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
From Simon Horman: Third Round of Renesas SH SCI Updates for v3.14 * Add Device Tree Support * Remove platform data mapbase and irqs fields * Remove platform data scbrr_algo_id field * tag 'renesas-sh-sci3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: serial: sh-sci: Add OF support serial: sh-sci: Add device tree bindings documentation serial: sh-sci: Remove platform data mapbase and irqs fields serial: sh-sci: Remove platform data scbrr_algo_id field Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/r8a7790-clock.h100
-rw-r--r--include/dt-bindings/clock/r8a7791-clock.h105
-rw-r--r--include/linux/serial_sci.h36
3 files changed, 205 insertions, 36 deletions
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
new file mode 100644
index 000000000000..420f0b00ae1e
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -0,0 +1,100 @@
1/*
2 * Copyright 2013 Ideas On Board SPRL
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
11#define __DT_BINDINGS_CLOCK_R8A7790_H__
12
13/* CPG */
14#define R8A7790_CLK_MAIN 0
15#define R8A7790_CLK_PLL0 1
16#define R8A7790_CLK_PLL1 2
17#define R8A7790_CLK_PLL3 3
18#define R8A7790_CLK_LB 4
19#define R8A7790_CLK_QSPI 5
20#define R8A7790_CLK_SDH 6
21#define R8A7790_CLK_SD0 7
22#define R8A7790_CLK_SD1 8
23#define R8A7790_CLK_Z 9
24
25/* MSTP1 */
26#define R8A7790_CLK_TMU1 11
27#define R8A7790_CLK_TMU3 21
28#define R8A7790_CLK_TMU2 22
29#define R8A7790_CLK_CMT0 24
30#define R8A7790_CLK_TMU0 25
31#define R8A7790_CLK_VSP1_DU1 27
32#define R8A7790_CLK_VSP1_DU0 28
33#define R8A7790_CLK_VSP1_RT 30
34#define R8A7790_CLK_VSP1_SY 31
35
36/* MSTP2 */
37#define R8A7790_CLK_SCIFA2 2
38#define R8A7790_CLK_SCIFA1 3
39#define R8A7790_CLK_SCIFA0 4
40#define R8A7790_CLK_SCIFB0 6
41#define R8A7790_CLK_SCIFB1 7
42#define R8A7790_CLK_SCIFB2 16
43#define R8A7790_CLK_SYS_DMAC0 18
44#define R8A7790_CLK_SYS_DMAC1 19
45
46/* MSTP3 */
47#define R8A7790_CLK_TPU0 4
48#define R8A7790_CLK_MMCIF1 5
49#define R8A7790_CLK_SDHI3 11
50#define R8A7790_CLK_SDHI2 12
51#define R8A7790_CLK_SDHI1 13
52#define R8A7790_CLK_SDHI0 14
53#define R8A7790_CLK_MMCIF0 15
54#define R8A7790_CLK_SSUSB 28
55#define R8A7790_CLK_CMT1 29
56#define R8A7790_CLK_USBDMAC0 30
57#define R8A7790_CLK_USBDMAC1 31
58
59/* MSTP5 */
60#define R8A7790_CLK_THERMAL 22
61#define R8A7790_CLK_PWM 23
62
63/* MSTP7 */
64#define R8A7790_CLK_EHCI 3
65#define R8A7790_CLK_HSUSB 4
66#define R8A7790_CLK_HSCIF1 16
67#define R8A7790_CLK_HSCIF0 17
68#define R8A7790_CLK_SCIF1 20
69#define R8A7790_CLK_SCIF0 21
70#define R8A7790_CLK_DU2 22
71#define R8A7790_CLK_DU1 23
72#define R8A7790_CLK_DU0 24
73#define R8A7790_CLK_LVDS1 25
74#define R8A7790_CLK_LVDS0 26
75
76/* MSTP8 */
77#define R8A7790_CLK_VIN3 8
78#define R8A7790_CLK_VIN2 9
79#define R8A7790_CLK_VIN1 10
80#define R8A7790_CLK_VIN0 11
81#define R8A7790_CLK_ETHER 13
82#define R8A7790_CLK_SATA1 14
83#define R8A7790_CLK_SATA0 15
84
85/* MSTP9 */
86#define R8A7790_CLK_GPIO5 7
87#define R8A7790_CLK_GPIO4 8
88#define R8A7790_CLK_GPIO3 9
89#define R8A7790_CLK_GPIO2 10
90#define R8A7790_CLK_GPIO1 11
91#define R8A7790_CLK_GPIO0 12
92#define R8A7790_CLK_RCAN1 15
93#define R8A7790_CLK_RCAN0 16
94#define R8A7790_CLK_IICDVFS 26
95#define R8A7790_CLK_I2C3 28
96#define R8A7790_CLK_I2C2 29
97#define R8A7790_CLK_I2C1 30
98#define R8A7790_CLK_I2C0 31
99
100#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
new file mode 100644
index 000000000000..df1715b77f96
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2013 Ideas On Board SPRL
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
11#define __DT_BINDINGS_CLOCK_R8A7791_H__
12
13/* CPG */
14#define R8A7791_CLK_MAIN 0
15#define R8A7791_CLK_PLL0 1
16#define R8A7791_CLK_PLL1 2
17#define R8A7791_CLK_PLL3 3
18#define R8A7791_CLK_LB 4
19#define R8A7791_CLK_QSPI 5
20#define R8A7791_CLK_SDH 6
21#define R8A7791_CLK_SD0 7
22#define R8A7791_CLK_Z 8
23
24/* MSTP1 */
25#define R8A7791_CLK_TMU1 11
26#define R8A7791_CLK_TMU3 21
27#define R8A7791_CLK_TMU2 22
28#define R8A7791_CLK_CMT0 24
29#define R8A7791_CLK_TMU0 25
30#define R8A7791_CLK_VSP1_DU1 27
31#define R8A7791_CLK_VSP1_DU0 28
32#define R8A7791_CLK_VSP1_SY 31
33
34/* MSTP2 */
35#define R8A7791_CLK_SCIFA2 2
36#define R8A7791_CLK_SCIFA1 3
37#define R8A7791_CLK_SCIFA0 4
38#define R8A7791_CLK_SCIFB0 6
39#define R8A7791_CLK_SCIFB1 7
40#define R8A7791_CLK_SCIFB2 16
41#define R8A7791_CLK_DMAC 18
42
43/* MSTP3 */
44#define R8A7791_CLK_TPU0 4
45#define R8A7791_CLK_SDHI2 11
46#define R8A7791_CLK_SDHI1 12
47#define R8A7791_CLK_SDHI0 14
48#define R8A7791_CLK_MMCIF0 15
49#define R8A7791_CLK_SSUSB 28
50#define R8A7791_CLK_CMT1 29
51#define R8A7791_CLK_USBDMAC0 30
52#define R8A7791_CLK_USBDMAC1 31
53
54/* MSTP5 */
55#define R8A7791_CLK_THERMAL 22
56#define R8A7791_CLK_PWM 23
57
58/* MSTP7 */
59#define R8A7791_CLK_HSUSB 4
60#define R8A7791_CLK_HSCIF2 13
61#define R8A7791_CLK_SCIF5 14
62#define R8A7791_CLK_SCIF4 15
63#define R8A7791_CLK_HSCIF1 16
64#define R8A7791_CLK_HSCIF0 17
65#define R8A7791_CLK_SCIF3 18
66#define R8A7791_CLK_SCIF2 19
67#define R8A7791_CLK_SCIF1 20
68#define R8A7791_CLK_SCIF0 21
69#define R8A7791_CLK_DU1 23
70#define R8A7791_CLK_DU0 24
71#define R8A7791_CLK_LVDS0 26
72
73/* MSTP8 */
74#define R8A7791_CLK_VIN2 9
75#define R8A7791_CLK_VIN1 10
76#define R8A7791_CLK_VIN0 11
77#define R8A7791_CLK_ETHER 13
78#define R8A7791_CLK_SATA1 14
79#define R8A7791_CLK_SATA0 15
80
81/* MSTP9 */
82#define R8A7791_CLK_GPIO7 4
83#define R8A7791_CLK_GPIO6 5
84#define R8A7791_CLK_GPIO5 7
85#define R8A7791_CLK_GPIO4 8
86#define R8A7791_CLK_GPIO3 9
87#define R8A7791_CLK_GPIO2 10
88#define R8A7791_CLK_GPIO1 11
89#define R8A7791_CLK_GPIO0 12
90#define R8A7791_CLK_RCAN1 15
91#define R8A7791_CLK_RCAN0 16
92#define R8A7791_CLK_I2C5 25
93#define R8A7791_CLK_IICDVFS 26
94#define R8A7791_CLK_I2C4 27
95#define R8A7791_CLK_I2C3 28
96#define R8A7791_CLK_I2C2 29
97#define R8A7791_CLK_I2C1 30
98#define R8A7791_CLK_I2C0 31
99
100/* MSTP11 */
101#define R8A7791_CLK_SCIFA3 6
102#define R8A7791_CLK_SCIFA4 7
103#define R8A7791_CLK_SCIFA5 8
104
105#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index af414e1895a5..22b3640c9424 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -10,15 +10,6 @@
10 10
11#define SCIx_NOT_SUPPORTED (-1) 11#define SCIx_NOT_SUPPORTED (-1)
12 12
13enum {
14 SCBRR_ALGO_NONE, /* Compute sampling rate in the driver */
15 SCBRR_ALGO_1, /* clk / (16 * bps) */
16 SCBRR_ALGO_2, /* DIV_ROUND_CLOSEST(clk, 32 * bps) - 1 */
17 SCBRR_ALGO_3, /* clk / (8 * bps) */
18 SCBRR_ALGO_4, /* DIV_ROUND_CLOSEST(clk, 16 * bps) - 1 */
19 SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */
20};
21
22#define SCSCR_TIE (1 << 7) 13#define SCSCR_TIE (1 << 7)
23#define SCSCR_RIE (1 << 6) 14#define SCSCR_RIE (1 << 6)
24#define SCSCR_TE (1 << 5) 15#define SCSCR_TE (1 << 5)
@@ -59,17 +50,6 @@ enum {
59/* HSSRR HSCIF */ 50/* HSSRR HSCIF */
60#define HSCIF_SRE 0x8000 51#define HSCIF_SRE 0x8000
61 52
62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73enum { 53enum {
74 SCIx_PROBE_REGTYPE, 54 SCIx_PROBE_REGTYPE,
75 55
@@ -88,19 +68,6 @@ enum {
88 SCIx_NR_REGTYPES, 68 SCIx_NR_REGTYPES,
89}; 69};
90 70
91#define SCIx_IRQ_MUXED(irq) \
92{ \
93 [SCIx_ERI_IRQ] = (irq), \
94 [SCIx_RXI_IRQ] = (irq), \
95 [SCIx_TXI_IRQ] = (irq), \
96 [SCIx_BRI_IRQ] = (irq), \
97}
98
99#define SCIx_IRQ_IS_MUXED(port) \
100 ((port)->irqs[SCIx_ERI_IRQ] == \
101 (port)->irqs[SCIx_RXI_IRQ]) || \
102 ((port)->irqs[SCIx_ERI_IRQ] && \
103 ((port)->irqs[SCIx_RXI_IRQ] < 0))
104/* 71/*
105 * SCI register subset common for all port types. 72 * SCI register subset common for all port types.
106 * Not all registers will exist on all parts. 73 * Not all registers will exist on all parts.
@@ -129,14 +96,11 @@ struct plat_sci_port_ops {
129 * Platform device specific platform_data struct 96 * Platform device specific platform_data struct
130 */ 97 */
131struct plat_sci_port { 98struct plat_sci_port {
132 unsigned long mapbase; /* resource base */
133 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
134 unsigned int type; /* SCI / SCIF / IRDA / HSCIF */ 99 unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
135 upf_t flags; /* UPF_* flags */ 100 upf_t flags; /* UPF_* flags */
136 unsigned long capabilities; /* Port features/capabilities */ 101 unsigned long capabilities; /* Port features/capabilities */
137 102
138 unsigned int sampling_rate; 103 unsigned int sampling_rate;
139 unsigned int scbrr_algo_id; /* SCBRR calculation algo */
140 unsigned int scscr; /* SCSCR initialization */ 104 unsigned int scscr; /* SCSCR initialization */
141 105
142 /* 106 /*
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-27 03:15:30 -0500