Merge tag 'clk-for-linus-3.18' of git://git.linaro.org/people/mike.turquette/linux

Pull clock tree updates from Mike Turquette:
 "The clk tree changes for 3.18 are dominated by clock drivers.  Mostly
  fixes and enhancements to existing drivers as well as new drivers.
  This tag contains a bit more arch code than I usually take due to some
  OMAP2+ changes.  Additionally it contains the restart notifier
  handlers which are merged as a dependency into several trees.

  The PXA changes are the only messy part.  Due to having a stable tree
  I had to revert one patch and follow up with one more fix near the tip
  of this tag.  Some dead code is introduced but it will soon become
  live code after 3.18-rc1 is released as the rest of the PXA family is
  converted over to the common clock framework.

  Another trend in this tag is that multiple vendors have started to
  push the complexity of changing their CPU frequency into the clock
  driver, whereas this used to be done in CPUfreq drivers.

  Changes to the clk core include a generic gpio-clock type and a
  clk_set_phase() function added to the top-level clk.h api.  Due to
  some confusion on the fbdev mailing list the kernel boot parameters
  documentation was updated to further explain the clk_ignore_unused
  parameter, which is often required by users of the simplefb driver.

  Finally some fixes to the locking around the clock debugfs stuff was
  done to prevent deadlocks when interacting with other subsystems."

* tag 'clk-for-linus-3.18' of git://git.linaro.org/people/mike.turquette/linux: (99 commits)
  clk: pxa clocks build system fix
  Revert "arm: pxa: Transition pxa27x to clk framework"
  clk: samsung: register restart handlers for s3c2412 and s3c2443
  clk: rockchip: add restart handler
  clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate
  doc/kernel-parameters.txt: clarify clk_ignore_unused
  arm: pxa: Transition pxa27x to clk framework
  dts: add devicetree bindings for pxa27x clocks
  clk: add pxa27x clock drivers
  arm: pxa: add clock pll selection bits
  clk: dts: document pxa clock binding
  clk: add pxa clocks infrastructure
  clk: gpio-gate: Ensure gpiod_ APIs are prototyped
  clk: ti: dra7-atl-clock: Mark the device as pm_runtime_irq_safe
  clk: ti: LLVMLinux: Move __init outside of type definition
  clk: ti: consider the fact that of_clk_get() might return an error
  clk: ti: dra7-atl-clock: fix a memory leak
  clk: ti: change clock init to use generic of_clk_init
  clk: hix5hd2: add I2C clocks
  clk: hix5hd2: add watchdog0 clocks
  ...

14 files changed, 337 insertions, 7 deletions

diff --git a/include/asm-generic/clkdev.h b/include/asm-generic/clkdev.h
index 90a32a61dd21..4ff334749ed5 100644
--- a/include/asm-generic/clkdev.h
+++ b/include/asm-generic/clkdev.h
@@ -15,10 +15,12 @@
 
 #include <linux/slab.h>
 
+#ifndef CONFIG_COMMON_CLK
 struct clk;
 
 static inline int __clk_get(struct clk *clk) { return 1; }
 static inline void __clk_put(struct clk *clk) { }
+#endif
 
 static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
 {
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index b535e9da7de6..961b9c130ea9 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -255,4 +255,31 @@
  */
 #define CLK_NR_CLKS                     248
 
+/*
+ * CMU DMC
+ */
+
+#define CLK_FOUT_BPLL                   1
+#define CLK_FOUT_EPLL                   2
+
+/* Muxes */
+#define CLK_MOUT_MPLL_MIF               8
+#define CLK_MOUT_BPLL                   9
+#define CLK_MOUT_DPHY                   10
+#define CLK_MOUT_DMC_BUS                11
+#define CLK_MOUT_EPLL                   12
+
+/* Dividers */
+#define CLK_DIV_DMC                     16
+#define CLK_DIV_DPHY                    17
+#define CLK_DIV_DMC_PRE                 18
+#define CLK_DIV_DMCP                    19
+#define CLK_DIV_DMCD                    20
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define NR_CLKS_DMC                     21
+
 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 459bd2bd411f..34fe28c622d0 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -115,11 +115,11 @@
 #define CLK_SMMU_MFCR           275
 #define CLK_G3D                 276
 #define CLK_G2D                 277
-#define CLK_ROTATOR             278 /* Exynos4210 only */
-#define CLK_MDMA                279 /* Exynos4210 only */
-#define CLK_SMMU_G2D            280 /* Exynos4210 only */
-#define CLK_SMMU_ROTATOR        281 /* Exynos4210 only */
-#define CLK_SMMU_MDMA           282 /* Exynos4210 only */
+#define CLK_ROTATOR             278
+#define CLK_MDMA                279
+#define CLK_SMMU_G2D            280
+#define CLK_SMMU_ROTATOR        281
+#define CLK_SMMU_MDMA           282
 #define CLK_FIMD0               283
 #define CLK_MIE0                284
 #define CLK_MDNIE0              285 /* Exynos4412 only */
@@ -234,6 +234,8 @@
 #define CLK_MOUT_G3D1           393
 #define CLK_MOUT_G3D            394
 #define CLK_ACLK400_MCUISP      395 /* Exynos4x12 only */
+#define CLK_MOUT_HDMI           396
+#define CLK_MOUT_MIXER          397
 
 /* gate clocks - ppmu */
 #define CLK_PPMULEFT            400
diff --git a/include/dt-bindings/clock/hix5hd2-clock.h b/include/dt-bindings/clock/hix5hd2-clock.h
index aad579a75802..fd29c174ba63 100644
--- a/include/dt-bindings/clock/hix5hd2-clock.h
+++ b/include/dt-bindings/clock/hix5hd2-clock.h
@@ -46,6 +46,7 @@
 #define HIX5HD2_SFC_MUX                 64
 #define HIX5HD2_MMC_MUX                 65
 #define HIX5HD2_FEPHY_MUX               66
+#define HIX5HD2_SD_MUX                  67
 
 /* gate clocks */
 #define HIX5HD2_SFC_RST                 128
@@ -53,6 +54,32 @@
 #define HIX5HD2_MMC_CIU_CLK             130
 #define HIX5HD2_MMC_BIU_CLK             131
 #define HIX5HD2_MMC_CIU_RST             132
+#define HIX5HD2_FWD_BUS_CLK             133
+#define HIX5HD2_FWD_SYS_CLK             134
+#define HIX5HD2_MAC0_PHY_CLK            135
+#define HIX5HD2_SD_CIU_CLK              136
+#define HIX5HD2_SD_BIU_CLK              137
+#define HIX5HD2_SD_CIU_RST              138
+#define HIX5HD2_WDG0_CLK                139
+#define HIX5HD2_WDG0_RST                140
+#define HIX5HD2_I2C0_CLK                141
+#define HIX5HD2_I2C0_RST                142
+#define HIX5HD2_I2C1_CLK                143
+#define HIX5HD2_I2C1_RST                144
+#define HIX5HD2_I2C2_CLK                145
+#define HIX5HD2_I2C2_RST                146
+#define HIX5HD2_I2C3_CLK                147
+#define HIX5HD2_I2C3_RST                148
+#define HIX5HD2_I2C4_CLK                149
+#define HIX5HD2_I2C4_RST                150
+#define HIX5HD2_I2C5_CLK                151
+#define HIX5HD2_I2C5_RST                152
+
+/* complex */
+#define HIX5HD2_MAC0_CLK                192
+#define HIX5HD2_MAC1_CLK                193
+#define HIX5HD2_SATA_CLK                194
+#define HIX5HD2_USB_CLK                 195
 
 #define HIX5HD2_NR_CLKS                 256
 #endif  /* __DTS_HIX5HD2_CLOCK_H */
diff --git a/include/dt-bindings/clock/maxim,max77686.h b/include/dt-bindings/clock/maxim,max77686.h
new file mode 100644
index 000000000000..7b28b0905869
--- /dev/null
+++ b/include/dt-bindings/clock/maxim,max77686.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77686 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77686_CLK_AP         0
+#define MAX77686_CLK_CP         1
+#define MAX77686_CLK_PMIC       2
+
+/* Total number of clocks. */
+#define MAX77686_CLKS_NUM               (MAX77686_CLK_PMIC + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H */
diff --git a/include/dt-bindings/clock/maxim,max77802.h b/include/dt-bindings/clock/maxim,max77802.h
new file mode 100644
index 000000000000..997312edcbb5
--- /dev/null
+++ b/include/dt-bindings/clock/maxim,max77802.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77802 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77802_CLK_32K_AP             0
+#define MAX77802_CLK_32K_CP             1
+
+/* Total number of clocks. */
+#define MAX77802_CLKS_NUM               (MAX77802_CLK_32K_CP + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */
diff --git a/include/dt-bindings/clock/pxa-clock.h b/include/dt-bindings/clock/pxa-clock.h
new file mode 100644
index 000000000000..e65803b1dc7e
--- /dev/null
+++ b/include/dt-bindings/clock/pxa-clock.h
@@ -0,0 +1,77 @@
+/*
+ * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre
+ * Copyright (C) 2014 Robert Jarzmik
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__
+#define __DT_BINDINGS_CLOCK_PXA2XX_H__
+
+#define CLK_NONE 0
+#define CLK_1WIRE 1
+#define CLK_AC97 2
+#define CLK_AC97CONF 3
+#define CLK_ASSP 4
+#define CLK_BOOT 5
+#define CLK_BTUART 6
+#define CLK_CAMERA 7
+#define CLK_CIR 8
+#define CLK_CORE 9
+#define CLK_DMC 10
+#define CLK_FFUART 11
+#define CLK_FICP 12
+#define CLK_GPIO 13
+#define CLK_HSIO2 14
+#define CLK_HWUART 15
+#define CLK_I2C 16
+#define CLK_I2S 17
+#define CLK_IM 18
+#define CLK_INC 19
+#define CLK_ISC 20
+#define CLK_KEYPAD 21
+#define CLK_LCD 22
+#define CLK_MEMC 23
+#define CLK_MEMSTK 24
+#define CLK_MINI_IM 25
+#define CLK_MINI_LCD 26
+#define CLK_MMC 27
+#define CLK_MMC1 28
+#define CLK_MMC2 29
+#define CLK_MMC3 30
+#define CLK_MSL 31
+#define CLK_MSL0 32
+#define CLK_MVED 33
+#define CLK_NAND 34
+#define CLK_NSSP 35
+#define CLK_OSTIMER 36
+#define CLK_PWM0 37
+#define CLK_PWM1 38
+#define CLK_PWM2 39
+#define CLK_PWM3 40
+#define CLK_PWRI2C 41
+#define CLK_PXA300_GCU 42
+#define CLK_PXA320_GCU 43
+#define CLK_SMC 44
+#define CLK_SSP 45
+#define CLK_SSP1 46
+#define CLK_SSP2 47
+#define CLK_SSP3 48
+#define CLK_SSP4 49
+#define CLK_STUART 50
+#define CLK_TOUCH 51
+#define CLK_TPM 52
+#define CLK_UDC 53
+#define CLK_USB 54
+#define CLK_USB2 55
+#define CLK_USBH 56
+#define CLK_USBHOST 57
+#define CLK_USIM 58
+#define CLK_USIM1 59
+#define CLK_USMI0 60
+#define CLK_MAX 61
+
+#endif
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
index 750ee60e75fb..6a370503c954 100644
--- a/include/dt-bindings/clock/rk3188-cru-common.h
+++ b/include/dt-bindings/clock/rk3188-cru-common.h
@@ -20,6 +20,7 @@
 #define PLL_GPLL                4
 #define CORE_PERI               5
 #define CORE_L2C                6
+#define ARMCLK                  7
 
 /* sclk gates (special clocks) */
 #define SCLK_UART0              64
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index ebcb460ea4ad..100a08c47692 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -19,6 +19,7 @@
 #define PLL_CPLL                3
 #define PLL_GPLL                4
 #define PLL_NPLL                5
+#define ARMCLK                  6
 
 /* sclk gates (special clocks) */
 #define SCLK_GPU                64
@@ -61,6 +62,15 @@
 #define SCLK_LCDC_PWM1          101
 #define SCLK_MAC_RX             102
 #define SCLK_MAC_TX             103
+#define SCLK_EDP_24M            104
+#define SCLK_EDP                105
+#define SCLK_RGA                106
+#define SCLK_ISP                107
+#define SCLK_ISP_JPE            108
+#define SCLK_HDMI_HDCP          109
+#define SCLK_HDMI_CEC           110
+#define SCLK_HEVC_CABAC         111
+#define SCLK_HEVC_CORE          112
 
 #define DCLK_VOP0               190
 #define DCLK_VOP1               191
@@ -75,6 +85,16 @@
 #define ACLK_VOP1               198
 #define ACLK_CRYPTO             199
 #define ACLK_RGA                200
+#define ACLK_RGA_NIU            201
+#define ACLK_IEP                202
+#define ACLK_VIO0_NIU           203
+#define ACLK_VIP                204
+#define ACLK_ISP                205
+#define ACLK_VIO1_NIU           206
+#define ACLK_HEVC               207
+#define ACLK_VCODEC             208
+#define ACLK_CPU                209
+#define ACLK_PERI               210
 
 /* pclk gates */
 #define PCLK_GPIO0              320
@@ -112,6 +132,15 @@
 #define PCLK_PS2C               352
 #define PCLK_TIMER              353
 #define PCLK_TZPC               354
+#define PCLK_EDP_CTRL           355
+#define PCLK_MIPI_DSI0          356
+#define PCLK_MIPI_DSI1          357
+#define PCLK_MIPI_CSI           358
+#define PCLK_LVDS_PHY           359
+#define PCLK_HDMI_CTRL          360
+#define PCLK_VIO2_H2P           361
+#define PCLK_CPU                362
+#define PCLK_PERI               363
 
 /* hclk gates */
 #define HCLK_GPS                448
@@ -137,8 +166,16 @@
 #define HCLK_IEP                468
 #define HCLK_ISP                469
 #define HCLK_RGA                470
+#define HCLK_VIO_AHB_ARBI       471
+#define HCLK_VIO_NIU            472
+#define HCLK_VIP                473
+#define HCLK_VIO2_H2P           474
+#define HCLK_HEVC               475
+#define HCLK_VCODEC             476
+#define HCLK_CPU                477
+#define HCLK_PERI               478
 
-#define CLK_NR_CLKS             (HCLK_RGA + 1)
+#define CLK_NR_CLKS             (HCLK_PERI + 1)
 
 /* soft-reset indices */
 #define SRST_CORE0              0
@@ -276,3 +313,46 @@
 #define SRST_USBHOST1_CON       140
 #define SRST_USB_ADP            141
 #define SRST_ACC_EFUSE          142
+
+#define SRST_CORESIGHT          144
+#define SRST_PD_CORE_AHB_NOC    145
+#define SRST_PD_CORE_APB_NOC    146
+#define SRST_PD_CORE_MP_AXI     147
+#define SRST_GIC                148
+#define SRST_LCDC_PWM0          149
+#define SRST_LCDC_PWM1          150
+#define SRST_VIO0_H2P_BRG       151
+#define SRST_VIO1_H2P_BRG       152
+#define SRST_RGA_H2P_BRG        153
+#define SRST_HEVC               154
+#define SRST_TSADC              159
+
+#define SRST_DDRPHY0            160
+#define SRST_DDRPHY0_APB        161
+#define SRST_DDRCTRL0           162
+#define SRST_DDRCTRL0_APB       163
+#define SRST_DDRPHY0_CTRL       164
+#define SRST_DDRPHY1            165
+#define SRST_DDRPHY1_APB        166
+#define SRST_DDRCTRL1           167
+#define SRST_DDRCTRL1_APB       168
+#define SRST_DDRPHY1_CTRL       169
+#define SRST_DDRMSCH0           170
+#define SRST_DDRMSCH1           171
+#define SRST_CRYPTO             174
+#define SRST_C2C_HOST           175
+
+#define SRST_LCDC1_AXI          176
+#define SRST_LCDC1_AHB          177
+#define SRST_LCDC1_DCLK         178
+#define SRST_UART0              179
+#define SRST_UART1              180
+#define SRST_UART2              181
+#define SRST_UART3              182
+#define SRST_UART4              183
+#define SRST_SIMC               186
+#define SRST_PS2C               187
+#define SRST_TSP                188
+#define SRST_TSP_CLKIN0         189
+#define SRST_TSP_CLKIN1         190
+#define SRST_TSP_27M            191
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
index 8a4c5892890f..6bac637fd635 100644
--- a/include/dt-bindings/clock/tegra124-car.h
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -337,6 +337,10 @@
 #define TEGRA124_CLK_DSIB_MUX 310
 #define TEGRA124_CLK_SOR0_LVDS 311
 #define TEGRA124_CLK_XUSB_SS_DIV2 312
-#define TEGRA124_CLK_CLK_MAX 313
+
+#define TEGRA124_CLK_PLL_M_UD 313
+#define TEGRA124_CLK_PLL_C_UD 314
+
+#define TEGRA124_CLK_CLK_MAX 315
 
 #endif  /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index efbf70b9fd84..0ca5f6046920 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -46,8 +46,10 @@ struct clk {
         unsigned int            enable_count;
         unsigned int            prepare_count;
         unsigned long           accuracy;
+        int                     phase;
         struct hlist_head       children;
         struct hlist_node       child_node;
+        struct hlist_node       debug_node;
         unsigned int            notifier_count;
 #ifdef CONFIG_DEBUG_FS
         struct dentry           *dentry;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 411dd7eb2653..be21af149f11 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -13,6 +13,7 @@
 
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/of.h>
 
 #ifdef CONFIG_COMMON_CLK
 
@@ -129,6 +130,14 @@ struct dentry;
  *              set then clock accuracy will be initialized to parent accuracy
  *              or 0 (perfect clock) if clock has no parent.
  *
+ * @get_phase:  Queries the hardware to get the current phase of a clock.
+ *              Returned values are 0-359 degrees on success, negative
+ *              error codes on failure.
+ *
+ * @set_phase:  Shift the phase this clock signal in degrees specified
+ *              by the second argument. Valid values for degrees are
+ *              0-359. Return 0 on success, otherwise -EERROR.
+ *
  * @init:       Perform platform-specific initialization magic.
  *              This is not not used by any of the basic clock types.
  *              Please consider other ways of solving initialization problems
@@ -177,6 +186,8 @@ struct clk_ops {
                                     unsigned long parent_rate, u8 index);
         unsigned long   (*recalc_accuracy)(struct clk_hw *hw,
                                            unsigned long parent_accuracy);
+        int             (*get_phase)(struct clk_hw *hw);
+        int             (*set_phase)(struct clk_hw *hw, int degrees);
         void            (*init)(struct clk_hw *hw);
         int             (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
 };
@@ -488,6 +499,28 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
                 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
                 unsigned long flags);
 
+/***
+ * struct clk_gpio_gate - gpio gated clock
+ *
+ * @hw:         handle between common and hardware-specific interfaces
+ * @gpiod:      gpio descriptor
+ *
+ * Clock with a gpio control for enabling and disabling the parent clock.
+ * Implements .enable, .disable and .is_enabled
+ */
+
+struct clk_gpio {
+        struct clk_hw   hw;
+        struct gpio_desc *gpiod;
+};
+
+extern const struct clk_ops clk_gpio_gate_ops;
+struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
+                const char *parent_name, struct gpio_desc *gpio,
+                unsigned long flags);
+
+void of_gpio_clk_gate_setup(struct device_node *node);
+
 /**
  * clk_register - allocate a new clock, register it and return an opaque cookie
  * @dev: device that is registering this clock
diff --git a/include/linux/clk.h b/include/linux/clk.h
index afb44bfaf8d1..c7f258a81761 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -106,6 +106,25 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
  */
 long clk_get_accuracy(struct clk *clk);
 
+/**
+ * clk_set_phase - adjust the phase shift of a clock signal
+ * @clk: clock signal source
+ * @degrees: number of degrees the signal is shifted
+ *
+ * Shifts the phase of a clock signal by the specified degrees. Returns 0 on
+ * success, -EERROR otherwise.
+ */
+int clk_set_phase(struct clk *clk, int degrees);
+
+/**
+ * clk_get_phase - return the phase shift of a clock signal
+ * @clk: clock signal source
+ *
+ * Returns the phase shift of a clock node in degrees, otherwise returns
+ * -EERROR.
+ */
+int clk_get_phase(struct clk *clk);
+
 #else
 
 static inline long clk_get_accuracy(struct clk *clk)
@@ -113,6 +132,16 @@ static inline long clk_get_accuracy(struct clk *clk)
         return -ENOTSUPP;
 }
 
+static inline long clk_set_phase(struct clk *clk, int phase)
+{
+        return -ENOTSUPP;
+}
+
+static inline long clk_get_phase(struct clk *clk)
+{
+        return -ENOTSUPP;
+}
+
 #endif
 
 /**
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index e8d8a35034a5..f75acbf70e96 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -292,6 +292,7 @@ void omap2xxx_clkt_vps_init(void);
 void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
 void ti_dt_clocks_register(struct ti_dt_clk *oclks);
 void ti_dt_clk_init_provider(struct device_node *np, int index);
+void ti_dt_clk_init_retry_clks(void);
 void ti_dt_clockdomains_setup(void);
 int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
                       ti_of_clk_init_cb_t func);