diff options
| author | Josh Wu <josh.wu@atmel.com> | 2013-12-10 07:25:47 -0500 |
|---|---|---|
| committer | Mauro Carvalho Chehab <m.chehab@samsung.com> | 2013-12-18 03:55:48 -0500 |
| commit | bd6f27458b0c50469ba1bb0a53e5ad1ac9e950d5 (patch) | |
| tree | 0ebc5a4c23a44a09484d381cce4602d1520fdac2 /include | |
| parent | 135983e8b392b424c7c9e117a981ad21e7c26893 (diff) | |
[media] v4l: atmel-isi: Should clear bits before set the hardware register
In the ISI driver it reads the config register to get original value,
then set the correct FRATE_DIV and YCC_SWAP_MODE directly. This will
cause some bits overlap.
So we need to clear these bits first, then set correct value. This patch
fix it.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/media/atmel-isi.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/media/atmel-isi.h b/include/media/atmel-isi.h index 656823075709..2b023471ac89 100644 --- a/include/media/atmel-isi.h +++ b/include/media/atmel-isi.h | |||
| @@ -56,6 +56,7 @@ | |||
| 56 | #define ISI_CFG1_FRATE_DIV_6 (5 << 8) | 56 | #define ISI_CFG1_FRATE_DIV_6 (5 << 8) |
| 57 | #define ISI_CFG1_FRATE_DIV_7 (6 << 8) | 57 | #define ISI_CFG1_FRATE_DIV_7 (6 << 8) |
| 58 | #define ISI_CFG1_FRATE_DIV_8 (7 << 8) | 58 | #define ISI_CFG1_FRATE_DIV_8 (7 << 8) |
| 59 | #define ISI_CFG1_FRATE_DIV_MASK (7 << 8) | ||
| 59 | #define ISI_CFG1_DISCR (1 << 11) | 60 | #define ISI_CFG1_DISCR (1 << 11) |
| 60 | #define ISI_CFG1_FULL_MODE (1 << 12) | 61 | #define ISI_CFG1_FULL_MODE (1 << 12) |
| 61 | 62 | ||
| @@ -66,6 +67,7 @@ | |||
| 66 | #define ISI_CFG2_YCC_SWAP_MODE_1 (1 << 28) | 67 | #define ISI_CFG2_YCC_SWAP_MODE_1 (1 << 28) |
| 67 | #define ISI_CFG2_YCC_SWAP_MODE_2 (2 << 28) | 68 | #define ISI_CFG2_YCC_SWAP_MODE_2 (2 << 28) |
| 68 | #define ISI_CFG2_YCC_SWAP_MODE_3 (3 << 28) | 69 | #define ISI_CFG2_YCC_SWAP_MODE_3 (3 << 28) |
| 70 | #define ISI_CFG2_YCC_SWAP_MODE_MASK (3 << 28) | ||
| 69 | #define ISI_CFG2_IM_VSIZE_OFFSET 0 | 71 | #define ISI_CFG2_IM_VSIZE_OFFSET 0 |
| 70 | #define ISI_CFG2_IM_HSIZE_OFFSET 16 | 72 | #define ISI_CFG2_IM_HSIZE_OFFSET 16 |
| 71 | #define ISI_CFG2_IM_VSIZE_MASK (0x7FF << ISI_CFG2_IM_VSIZE_OFFSET) | 73 | #define ISI_CFG2_IM_VSIZE_MASK (0x7FF << ISI_CFG2_IM_VSIZE_OFFSET) |
