diff options
author | Andy Fleming <afleming@freescale.com> | 2005-10-28 20:46:27 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2005-10-29 00:42:28 -0400 |
commit | b37665e0ba1d3f05697bfae249b09a2e9cc95132 (patch) | |
tree | 22c80609e3254524038d5b690f1f886b0987f58d /include | |
parent | dd03d25fac90ee6f394874fb4e6995866304e4ba (diff) |
[PATCH] ppc32: 85xx PHY Platform Update
This patch updates the 85xx platform code to support the new PHY Layer.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <Kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-ppc/mpc85xx.h | 3 | ||||
-rw-r--r-- | include/linux/fsl_devices.h | 13 |
2 files changed, 12 insertions, 4 deletions
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h index 516984ee14b5..d98db980cd49 100644 --- a/include/asm-ppc/mpc85xx.h +++ b/include/asm-ppc/mpc85xx.h | |||
@@ -67,6 +67,8 @@ extern unsigned char __res[]; | |||
67 | #define MPC85xx_DMA3_SIZE (0x00080) | 67 | #define MPC85xx_DMA3_SIZE (0x00080) |
68 | #define MPC85xx_ENET1_OFFSET (0x24000) | 68 | #define MPC85xx_ENET1_OFFSET (0x24000) |
69 | #define MPC85xx_ENET1_SIZE (0x01000) | 69 | #define MPC85xx_ENET1_SIZE (0x01000) |
70 | #define MPC85xx_MIIM_OFFSET (0x24520) | ||
71 | #define MPC85xx_MIIM_SIZE (0x00018) | ||
70 | #define MPC85xx_ENET2_OFFSET (0x25000) | 72 | #define MPC85xx_ENET2_OFFSET (0x25000) |
71 | #define MPC85xx_ENET2_SIZE (0x01000) | 73 | #define MPC85xx_ENET2_SIZE (0x01000) |
72 | #define MPC85xx_ENET3_OFFSET (0x26000) | 74 | #define MPC85xx_ENET3_OFFSET (0x26000) |
@@ -132,6 +134,7 @@ enum ppc_sys_devices { | |||
132 | MPC85xx_eTSEC3, | 134 | MPC85xx_eTSEC3, |
133 | MPC85xx_eTSEC4, | 135 | MPC85xx_eTSEC4, |
134 | MPC85xx_IIC2, | 136 | MPC85xx_IIC2, |
137 | MPC85xx_MDIO, | ||
135 | }; | 138 | }; |
136 | 139 | ||
137 | /* Internal interrupts are all Level Sensitive, and Positive Polarity */ | 140 | /* Internal interrupts are all Level Sensitive, and Positive Polarity */ |
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index 70f54af87b9f..114d5d59f695 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h | |||
@@ -47,16 +47,21 @@ | |||
47 | struct gianfar_platform_data { | 47 | struct gianfar_platform_data { |
48 | /* device specific information */ | 48 | /* device specific information */ |
49 | u32 device_flags; | 49 | u32 device_flags; |
50 | u32 phy_reg_addr; | ||
51 | 50 | ||
52 | /* board specific information */ | 51 | /* board specific information */ |
53 | u32 board_flags; | 52 | u32 board_flags; |
54 | u32 phy_flags; | 53 | const char *bus_id; |
55 | u32 phyid; | ||
56 | u32 interruptPHY; | ||
57 | u8 mac_addr[6]; | 54 | u8 mac_addr[6]; |
58 | }; | 55 | }; |
59 | 56 | ||
57 | struct gianfar_mdio_data { | ||
58 | /* device specific information */ | ||
59 | u32 paddr; | ||
60 | |||
61 | /* board specific information */ | ||
62 | int irq[32]; | ||
63 | }; | ||
64 | |||
60 | /* Flags related to gianfar device features */ | 65 | /* Flags related to gianfar device features */ |
61 | #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001 | 66 | #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001 |
62 | #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 | 67 | #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 |