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authorPaul Mackerras <paulus@samba.org>2008-02-06 06:08:37 -0500
committerPaul Mackerras <paulus@samba.org>2008-02-06 06:08:37 -0500
commitb370b08274a25cf1e2015fb7ce65c43173c8156f (patch)
tree0c8f990148da4ca1275ac5471c93c519754f4aec /include
parent75e89b02e338d0db27f8e5d66642c7e2ae49c326 (diff)
parent7e25867fe8d705bcf707ef52004b669eb795d06d (diff)
Merge branch 'for-2.6.25' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc into for-2.6.25
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/cputable.h2
-rw-r--r--include/asm-powerpc/oprofile_impl.h2
-rw-r--r--include/asm-powerpc/reg.h4
-rw-r--r--include/asm-powerpc/reg_booke.h62
-rw-r--r--include/asm-powerpc/reg_fsl_emb.h72
5 files changed, 78 insertions, 64 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 528ef183c221..1e79673b7316 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -46,7 +46,7 @@ enum powerpc_oprofile_type {
46 PPC_OPROFILE_RS64 = 1, 46 PPC_OPROFILE_RS64 = 1,
47 PPC_OPROFILE_POWER4 = 2, 47 PPC_OPROFILE_POWER4 = 2,
48 PPC_OPROFILE_G4 = 3, 48 PPC_OPROFILE_G4 = 3,
49 PPC_OPROFILE_BOOKE = 4, 49 PPC_OPROFILE_FSL_EMB = 4,
50 PPC_OPROFILE_CELL = 5, 50 PPC_OPROFILE_CELL = 5,
51 PPC_OPROFILE_PA6T = 6, 51 PPC_OPROFILE_PA6T = 6,
52}; 52};
diff --git a/include/asm-powerpc/oprofile_impl.h b/include/asm-powerpc/oprofile_impl.h
index 938fefb4c4bc..95035c602ba6 100644
--- a/include/asm-powerpc/oprofile_impl.h
+++ b/include/asm-powerpc/oprofile_impl.h
@@ -54,7 +54,7 @@ struct op_powerpc_model {
54 int num_counters; 54 int num_counters;
55}; 55};
56 56
57extern struct op_powerpc_model op_model_fsl_booke; 57extern struct op_powerpc_model op_model_fsl_emb;
58extern struct op_powerpc_model op_model_rs64; 58extern struct op_powerpc_model op_model_rs64;
59extern struct op_powerpc_model op_model_power4; 59extern struct op_powerpc_model op_model_power4;
60extern struct op_powerpc_model op_model_7450; 60extern struct op_powerpc_model op_model_7450;
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 2408a29507e5..0d6238987df8 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -18,6 +18,10 @@
18#include <asm/reg_booke.h> 18#include <asm/reg_booke.h>
19#endif /* CONFIG_BOOKE || CONFIG_40x */ 19#endif /* CONFIG_BOOKE || CONFIG_40x */
20 20
21#ifdef CONFIG_FSL_EMB_PERFMON
22#include <asm/reg_fsl_emb.h>
23#endif
24
21#ifdef CONFIG_8xx 25#ifdef CONFIG_8xx
22#include <asm/reg_8xx.h> 26#include <asm/reg_8xx.h>
23#endif /* CONFIG_8xx */ 27#endif /* CONFIG_8xx */
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index 0405ef479814..cf54a3f31753 100644
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -9,68 +9,6 @@
9#ifndef __ASM_POWERPC_REG_BOOKE_H__ 9#ifndef __ASM_POWERPC_REG_BOOKE_H__
10#define __ASM_POWERPC_REG_BOOKE_H__ 10#define __ASM_POWERPC_REG_BOOKE_H__
11 11
12#ifndef __ASSEMBLY__
13/* Performance Monitor Registers */
14#define mfpmr(rn) ({unsigned int rval; \
15 asm volatile("mfpmr %0," __stringify(rn) \
16 : "=r" (rval)); rval;})
17#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
18#endif /* __ASSEMBLY__ */
19
20/* Freescale Book E Performance Monitor APU Registers */
21#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
22#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
23#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
24#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
25#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
26#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
27#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
28#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
29
30#define PMLCA_FC 0x80000000 /* Freeze Counter */
31#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
32#define PMLCA_FCU 0x20000000 /* Freeze in User */
33#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
34#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
35#define PMLCA_CE 0x04000000 /* Condition Enable */
36
37#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
38#define PMLCA_EVENT_SHIFT 16
39
40#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
41#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
42#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
43#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
44
45#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
46#define PMLCB_THRESHMUL_SHIFT 8
47
48#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
49#define PMLCB_THRESHOLD_SHIFT 0
50
51#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
52
53#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
54#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
55#define PMGC0_FCECE 0x20000000 /* Freeze countes on
56 Enabled Condition or
57 Event */
58
59#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
60#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
61#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
62#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
63#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
64#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
65#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
66#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
67#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
68#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
69#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
70#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
71#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
72
73
74/* Machine State Register (MSR) Fields */ 12/* Machine State Register (MSR) Fields */
75#define MSR_UCLE (1<<26) /* User-mode cache lock enable */ 13#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
76#define MSR_SPE (1<<25) /* Enable SPE */ 14#define MSR_SPE (1<<25) /* Enable SPE */
diff --git a/include/asm-powerpc/reg_fsl_emb.h b/include/asm-powerpc/reg_fsl_emb.h
new file mode 100644
index 000000000000..1e180a594589
--- /dev/null
+++ b/include/asm-powerpc/reg_fsl_emb.h
@@ -0,0 +1,72 @@
1/*
2 * Contains register definitions for the Freescale Embedded Performance
3 * Monitor.
4 */
5#ifdef __KERNEL__
6#ifndef __ASM_POWERPC_REG_FSL_EMB_H__
7#define __ASM_POWERPC_REG_FSL_EMB_H__
8
9#ifndef __ASSEMBLY__
10/* Performance Monitor Registers */
11#define mfpmr(rn) ({unsigned int rval; \
12 asm volatile("mfpmr %0," __stringify(rn) \
13 : "=r" (rval)); rval;})
14#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
15#endif /* __ASSEMBLY__ */
16
17/* Freescale Book E Performance Monitor APU Registers */
18#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
19#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
20#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
21#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
22#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
23#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
24#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
25#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
26
27#define PMLCA_FC 0x80000000 /* Freeze Counter */
28#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
29#define PMLCA_FCU 0x20000000 /* Freeze in User */
30#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
31#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
32#define PMLCA_CE 0x04000000 /* Condition Enable */
33
34#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
35#define PMLCA_EVENT_SHIFT 16
36
37#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
38#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
39#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
40#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
41
42#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
43#define PMLCB_THRESHMUL_SHIFT 8
44
45#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
46#define PMLCB_THRESHOLD_SHIFT 0
47
48#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
49
50#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
51#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
52#define PMGC0_FCECE 0x20000000 /* Freeze countes on
53 Enabled Condition or
54 Event */
55
56#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
57#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
58#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
59#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
60#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
61#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
62#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
63#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
64#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
65#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
66#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
67#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
68#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
69
70
71#endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */
72#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 00:54:28 -0500